Nonvolatile memory device
AssigneeMacronix International Co., Ltd.
InventorsYi-Chou Chen, Wei-Chih Chien, Feng-Ming Lee
Life of this patent
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Abstract
A memory device comprises an array of memory cells each capable of storing multiple bits of data. Each memory cell includes a programmable transistor in series with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.
Claims33
A memory device comprising an array of memory cells, at least one of the memory cells comprising:
- a transistor having a first terminal, a second terminal, and a gate terminal, the transistor being configured to be switchable between a plurality of different threshold voltages associated with respective memory states;
- and
- a resistance switching device connected in series with one of the first and second terminals of the transistor, the resistance switching device being configured to be switchable between a plurality of different resistances associated with respective memory states, wherein the resistance switching device comprises a first memory layer, a second memory layer, and a medium layer formed between the first memory layer and the second memory layer.
A memory device comprising:
- a first control line;
- a second control line;
- a memory cell in communication with the first and second control lines, the memory cell comprising:
- a transistor having a first terminal, a second terminal, and a gate terminal, the transistor being configured to be switchable between a plurality of different threshold voltages associated with respective memory states;
- and
- a resistance switching device connected in series between the first control line and the first terminal of the transistor, the resistance switching device being configured to be switchable between a plurality of different resistances associated with respective memory states, wherein the resistance switching device comprises a first memory layer, a second memory layer, and a medium layer formed between the first memory layer and the second memory layer.
A method of reading a memory cell of a semiconductor memory device, the method comprising:
- detecting a threshold voltage of a transistor of the memory cell, the transistor being configured to be switchable between a plurality of threshold voltages associated with respective memory states;
- and
- detecting a resistance of a resistance switching device of the memory cell, the resistance switching device being connected in series with the transistor and being configured to be switchable between a plurality of resistances associated with respective memory states, wherein the resistance switching device comprises a first memory layer, a second memory layer, and a medium layer formed between the first memory layer and the second memory layer.
Dependencies are inferred from the claim text.