Compact and accurate analog memory for CMOS imaging pixel detectors

Abstract

An analog memory circuit, i.e. a sample and hold circuit, wherein the source and the gate of the switching transistor is maintained at a same potential prior and after the sampling process using a transistor circuitry. The analog memory circuit comprises a memory capacitor (102) connected at a first end to a first port (104), which is connected a reference potential (106). A drain of a first transistor (108) —switch transistor—is connected to a second end of the memory capacitor (102). A source of the first transistor (108) is connected to a second port (110), which is connected to circuitry (112) for providing an input signal for storage in the memory capacitor (102), and a gate of the first transistor (108) is connected to a third port (114), which is connected to a first current sink (116). A source of a second transistor (118) is connected to the source of the first transistor (108) and a drain of the second transistor (118) is connected to the gate of the first transistor (108). The source of the first transistor (108) is connected to a source of a third transistor (120). A gate and a drain of the third transistor (120) are connected together to a gate of the second transistor (118) and to a fourth port (122), which is connected to a second current sink (124). According to the invention the feedthrough error is constant irrespective of the input signal level.

Dependencies are inferred from the claim text.