Gate driver with error blocking mechanism, method of operating the same, and display device having the same

A method of driving a gate driver in a display system designed to have a predetermined number of gate clock signal pulses during one frame and a predetermined duration of activation of a vertical synchronization start signal during the one frame, the method comprising:

• measuring the number of gate clock signals received by the gate driver in an interval where the vertical synchronization start signal supplied to gate driver is at an activation indicating, high level and in response to the measured number, either outputting a copy of the vertical synchronization start signal or a low-level signal;
• outputting a plurality of shift signals according to the copy of the vertical synchronization start signal and in response to the gate clock signal;
• shifting levels of the shift signals in response to the shift signals and outputting the level-shifted shift signals;
• and
• supplying the shift signals to gate lines.

A display device comprising:

• a display panel that displays an image;
• a timing controller that processes an externally input image signal and generates a plurality of control signals;
• a driving voltage generator that generates a plurality of driving voltages including a gate driving voltage and a data driving voltage;
• gate drivers each of which receives gate clock signals and which measures the number of gate clock signals in an interval where a received vertical synchronization start signal is at an activation indicating, high level during one frame, and in response to the measured number, selectively outputs either a copy of the vertical synchronization start signal or a low-level signal, and applies the gate driving voltage to gate lines in response to the selectively output copy of the vertical synchronization start signal;
• and
• a data driver that generates a data signal using the data driving voltage and applies the data signal to data lines.