Cyclic analog/digital converter

A cyclic analog/digital converter for processing an input signal having a first signal level and a second signal level, the first signal level including a noise component, and the second signal level including a signal component superimposed on the noise component, comprising:

• a gain stage including an operational amplifier circuit and first, second and third capacitors, the gain stage being capable of executing a process for noise cancellation to generate a difference signal indicating a difference between the first and second signal levels, and performing a process for cyclic A/D conversion of the difference signal;
• a sub A/D converter circuit receiving a signal from an output of the operational amplifier circuit;
• a logic circuit connected to the sub A/D converter circuit;
• a D/A converter circuit operable in accordance with a control signal from the logic circuit;
• and
• a timing circuit for controlling operations of the process for noise cancellation and the process for cyclic A/D conversion in the gain stage,
• in the process for noise cancellation, the gain stage sampling either one of the first and second signal levels into a first sampling capacitor, and, in response to reception of another of the first and second signal levels through the first sampling capacitor at an input of the operational amplifier circuit to which a first feedback capacitor is connected, the gain stage generating the difference signal at an output of the operational amplifier circuit and storing the difference signal in the first sampling capacitor and the first feedback capacitor,
• in the process for cyclic A/D conversion, the gain stage receiving a signal from the D/A converter circuit through a second sampling capacitor at the input of the operational amplifier circuit to which a second feedback capacitor is connected, to generate an operation value at the output of the operational amplifier circuit, and storing the operation value in the second sampling capacitor,
• the process for noise cancellation including first and second process modes which are exclusively executable,
• the timing circuit selecting an operation in the first and second process modes of the gain stage and controlling the operation of the selected process mode,
• a first gain of the gain stage in the first process mode being defined by a ratio of a capacitance of the third capacitor and the sum of capacitances of the first and second capacitors,
• a second gain of the gain stage in the second process mode being defined by a ratio of the capacitance of the third capacitor and the capacitance of the first capacitor, and
• the gain stage comprising:
• first switch means for providing a connection of the first capacitor such that the second sampling capacitor is composed of the first capacitor and for providing a connection of the second and third capacitors such that the second feedback capacitor is composed of the second and third capacitors;
• second switch means for providing a connection of the first and second capacitors such that the first sampling capacitor is composed of the first and second capacitors and for providing a connection of the third capacitor such that the first feedback capacitor is composed of the third capacitor;
• and
• third switch means for providing a connection of the first capacitor such that the first sampling capacitor is composed of the first capacitor and providing a connection of the third capacitor such that the first feedback capacitor is composed of the third capacitor, and for providing a parallel connection of the second capacitor to the first sampling capacitor for sampling of the difference signal.

A cyclic analog/digital converter for processing an input signal having a first signal level and a second signal level, the first signal level including a noise component, and the second signal level including a signal component superimposed on the noise component, comprising:

• a gain stage including an operational amplifier circuit and first, second and third capacitors, the gain stage being capable of executing a process for noise cancellation for generating a difference signal, and performing a process for cyclic A/D conversion of the difference signal, the difference signal indicating a difference between the first and second signal levels;
• a sub A/D converter circuit receiving a signal from an output of the operational amplifier circuit;
• a logic circuit connected to the sub A/D converter circuit;
• a D/A converter circuit operable in accordance with a control signal from the logic circuit;
• and
• a timing circuit for controlling operations of the process for noise cancellation and the process for cyclic A/D conversion of the gain stage,
• in the process for noise cancellation, the gain stage sampling either one of the first and second signal levels into a first sampling capacitor, and, in response to reception of another of the first and second signal levels through the first sampling capacitor at an input of the operational amplifier circuit to which a first feedback capacitor is connected, the gain stage generating the difference signal at an output of the operational amplifier circuit and storing the difference signal in the first sampling capacitor and the first feedback capacitor,
• in the process for cyclic A/D conversion, the gain stage receiving a signal from the D/A converter circuit through a second sampling capacitor at the input of the operational amplifier circuit to which a second feedback capacitor is connected, to generate an operation value at the output of the operational amplifier circuit, and storing the operation value in the second sampling capacitor,
• the process for noise cancellation including first and third process modes which are exclusively executable,
• the timing circuit selecting an operation in the first and third process modes of the gain stage and controlling the selected operation of the process for noise cancellation,
• a first gain of the gain stage in the first process mode being defined by a ratio of a capacitance of the third capacitor and the sum of capacitances of the first and second capacitors,
• a third gain of the gain stage in the third process mode being defined by a ratio of the sum of the capacitances of the second and third capacitors and the capacitance of the first capacitor, and
• the gain stage comprising:
• first switch means for providing a connection of the first capacitor such that the second sampling capacitor is composed of the first capacitor and for providing a connection of the second and third capacitors such that the first feedback capacitor is composed of the second and third capacitors;
• second switch means for providing a connection of the first and second capacitors such that the first sampling capacitor is composed of the first and second capacitors and for providing a connection of the third capacitor such that the first feedback capacitor is composed of the third capacitor;
• and
• fourth switch means for providing a connection of the first capacitor such that the first sampling capacitor is composed of the first capacitor and for providing a connection of the second and third capacitors such that the first feedback capacitor is composed of the second and third capacitors.