Duty-cycle feedback charge pump

A locked loop with a duty-cycle feedback charge pump comprising:

• a phase detector having a first input to accept a data signal having a first frequency, a second input to accept a reference clock having the first frequency, and an output to supply a phase detector signal with a change in duty cycle proportional to a change in phase difference between the data signal and the reference clock;
• a charge pump including:
• a reference charge pump having an input interface to accept the phase detector signal, an interface to accept a duty-cycle feedback signal, and an interface to supply a control voltage;
• and,
• a replica charge pump having an interface to accept the phase detector signal and an interface to supply the duty-cycle feedback signal;
• a loop filter having an input to accept the control voltage and an output to supply a conditioned control voltage;
• a voltage controlled phase operator having an input to accept the conditioned control voltage and an output to supply a voltage controlled phase operator signal with a phase responsive to the conditioned control voltage;
• wherein the reference charge pump includes:
• a first p-channel metal-oxide semiconductor (PMOS) with a source connected to a first dc voltage and a gate connected to accept the phase detector signal;
• a second PMOS with a source connected to a drain of the first PMOS, a gate connected to accept the duty-cycle feedback signal, and a drain connected to supply the control voltage;
• a first n-channel MOS (NMOS) having a drain connected to supply the control voltage and a gate connected to a second dc voltage, having a potential less than, or equal to the first dc voltage;
• a second NMOS having a drain connected to a source of the first NMOS, a gate accepting the phase detector signal, and a source connected to a third dc voltage, less than or equal to the second dc voltage;
• a first capacitor having a first terminal connected to the control voltage and a second terminal connected to a dc voltage;
• wherein the replica charge pump includes:
• an inverter having an input to accept the phase detector signal, and an output to supply an inverted phase detector signal;
• a third PMOS with a source connected to the first dc voltage and a gate connected to accept the inverted phase detector signal;
• a fourth PMOS with a source connected to a drain of the third PMOS, and a gate and a drain connected to the duty-cycle feedback signal;
• a third NMOS having a drain connected to supply the duty-cycle feedback signal and a gate connected to the second dc voltage;
• a fourth NMOS having a drain connected to a source of the third NMOS, a gate connected to accept the inverted phase detector signal, and a source connected to the third dc voltage;
• and,
• a second capacitor having a first terminal connected to the duty-cycle feedback signal and a second terminal connected to a dc voltage.

A duty-cycle feedback charge pump comprising:

• a reference charge pump having an interface to accept an input signal, an interface to accept a duty-cycle feedback signal, and an interface to supply an output signal;
• a replica charge pump having an interface to accept the input signal and an interface to supply the duty-cycle feedback signal;
• wherein the reference charge pump includes:
• a first PMOS with a source connected to a first dc voltage and a gate connected to accept the input signal;
• a second PMOS with a source connected to a drain of the first PMOS, a gate connected to a second dc voltage having a potential less than, or equal to the first dc voltage, and a drain connected to supply the output signal;
• a first NMOS having a drain connected to supply the output signal and a gate connected to accept the duty-cycle feedback signal;
• a second NMOS having a drain connected to a source of the first NMOS, a gate accepting the input signal, and a source connected to a third dc voltage, having a potential less than or equal to the second dc voltage;
• a first capacitor having a first terminal connected to the output signal and a second terminal connected to a dc voltage;
• wherein the replica charge pump includes:
• an inverter having an input to accept the input signal, and an output to supply the inverted input signal;
• a third PMOS with a source connected to the first dc voltage and a gate connected to accept the inverted input signal;
• a fourth PMOS with a source connected to a drain of the third PMOS, and a gate connected to the second dc voltage, and a drain connected to the duty-cycle feedback signal;
• a third NMOS having a gate and drain connected to the duty-cycle feedback signal;
• a fourth NMOS having a drain connected to a source of the third NMOS, a gate connected to accept the inverted input signal, and a source connected to the third dc voltage;
• and,
• a second capacitor having a first terminal connected to the duty-cycle feedback signal and a second terminal connected to a dc voltage.