RF buffer circuit with dynamic biasing
AssigneeQUALCOMM Incorporated
InventorsRangarajan Rajagopalan, Mishra Chinmaya
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Abstract
An RF buffer circuit for a voltage controlled oscillator (VCO) includes dynamic biasing circuitry to selectively flip the phase of the output voltage waveform. In a CMOS implementation, a PMOS/NMOS pair is employed in an output path. During a high (voltage) swing mode condition, the phase of the output is flipped such that the output waveform is in phase with the voltages appearing at the gates of the PMOS/NMOS pair. The technique thereby reduces peak gate-to-drain voltages and allows for improved reliability of the MOS devices in a configuration amenable to low phase noise and low power consumption.
Claims28
An RF buffer circuit comprising:
- first and second transistors;
- and
- dynamic biasing circuitry such that a buffered output voltage across the first and second transistors is substantially in-phase with an oscillating voltage at an input terminal of the first or second transistors, or substantially out of phase with said oscillating voltage, on the basis of an input voltage swing condition, set by an amplitude detector/controller having a comparator, at one or the other of the first and second transistors.
An RF buffer circuit for coupling to an output of a VCO core circuit, the RF buffer circuit including two buffer circuit portions, each buffer circuit portion comprising:
- means for detecting a high swing mode condition and a low swing mode condition at plural input terminals thereof;
- and
- an amplitude detector/controller, including a comparator responsive to the detected swing mode condition, to set the biasing voltage of the RF buffer circuit so as to phase align a voltage at an output terminal to a voltage at a biasing input terminal.
An RF buffer circuit comprising:
- first and second circuit portions having respective input terminals at which first and second oscillating voltages are applied, respectively;
- each circuit portion comprising:
- first and second transistors coupled in series, wherein a first output terminal of the first transistor is coupled to a first output terminal of the second transistor at a first output terminal of the buffer circuit providing a buffered oscillating output voltage;
- first and second capacitors coupled between the input terminal and respective gate terminals of the first and second transistors;
- and
- dynamic biasing circuitry to dynamically bias a second output terminal of the first transistor and a second output terminal of the second transistor, using an amplitude detector/controller having a comparator, to phase align the buffered oscillating output voltage with oscillating voltages at the gate terminals of the first and second transistors.
An RF buffer circuit comprising:
- first and second circuit portions having respective input terminals at which first and second oscillating voltages are applied, respectively;
- each circuit part comprising:
- first and second MOS devices coupled in series, wherein a first output terminal of the first MOS device is coupled to a first output terminal of the second MOS device at a first output terminal of the RF buffer circuit providing a buffered oscillating output voltage;
- first and second capacitors coupled between the input terminal and respective gate terminals of the first and second MOS devices;
- and
- dynamic biasing circuitry including an amplitude detector/controller having a comparator coupled to the second terminals of the first and second MOS devices, wherein (i) during a high swing mode condition as detected by the comparator, the second output terminal of the first MOS device is biased at a first level of low potential and the second output terminal of the second MOS device is biased at a first level of high potential, and (ii) during a low swing mode condition as detected by the comparator, the second output terminal of the first MOS device is biased at a second level of high potential and the second output of the first MOS device is biased at a second level of low potential.
Dependencies are inferred from the claim text.