US 8,148,798 B2Granted

Semiconductor device and method for manufacturing the same

AssigneeFujitsu Semiconductor Limited

InventorTakahiro Yamagata

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Abstract

The semiconductor device includes a capacitor 36 formed over a semiconductor substrate 10 and including a lower electrode 30, a dielectric film 32 and an upper electrode 34; a first insulation film 58 formed above the capacitor 36; a first interconnection 88a formed over the first insulation film 68; a second insulation film 90 formed over the first insulation film 68 and over the first interconnection 88a; an electrode pad 102 formed over the second insulation film 90: and a monolithic conductor 100 buried in the second insulation film 90 immediately below the electrode pad 102 and buried through the second insulation film 90 down to a part of at least the first insulation layer 68.

Claims10

Dependent claims

A semiconductor device comprising:

a capacitor formed over a semiconductor substrate and including a lower electrode, a dielectric film formed over the lower electrode and an upper electrode formed over the dielectric film;
a first insulation film formed over the capacitor;
a first interconnection formed over the first insulation film;
a second insulation film formed over the first insulation film and over the first interconnection;
an electrode pad formed over the second insulation film;
an opening formed continuously in the second insulation film and in the first insulation film below the electrode pad, the second insulation film and the first insulation film being penetrated by the opening;
and
a conductor plug buried in the opening, a length of the conductor plug being larger than at least a thickness of the second insulation film, and a diameter of the conductor plug being larger than a diameter of another conductor plug connected to the first interconnection.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/205,495Filed 5 Sep 2008 · continuation
Priority: 8 Mar 2006
Published: US 2009/0001515 A11 Jan 2009
Granted: 3 Apr 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification22 codes

H10D 88/00
Three-dimensional [3d] integrated devices
H10B 53/40
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors: characterised by the peripheral circuit region
H10D 1/682
Capacitors having no potential barriers: having dielectrics comprising perovskite structures
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe

Family

PCT/JP2006/304503Parent of this continuation · filed 8 Mar 2006
US 2009/0001515 A1Pre-grant publication · published 1 Jan 2009
US 8,148,798 B2This patent

From the US filing history. Foreign family members aren’t listed.

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