Devices and systems relating to a memory cell having a floating body

A memory device, comprising:

• a memory array including a plurality of memory cells, each memory cell comprising:
• a transistor overlying an insulation layer and comprising a drain region and a source region adjacent the insulation layer;
• a floating body having a first region adjacent the drain region and the source region, a second region configured as a charge storage region distant from the first region, wherein the insulation layer extends into the floating body to define a passage between the first region and the second region, the passage having a cross-sectional area that is less than individual cross-sectional areas of both the first region and the second region;
• and
• a bias gate at least partially surrounding the second region and configured to be operably coupled to a bias voltage.

An electronic system, comprising:

• at least one processor;
• and
• at least one memory device including a plurality of memory cells, each memory cell comprising:
• a transistor having a drain region and a source region overlying and adjacent to an insulation layer;
• a first region overlying the insulation layer and positioned between the source region and the drain region;
• a second region configured as a charge storage region comprising silicon and remotely positioned from the first region;
• a passage extending from the first region through the insulation layer to the second region, wherein the passage has a narrower horizontal length than individual horizontal lengths of both the first region and the second region;
• and
• a bias gate at least partially surrounding the second region and adapted for operable coupling to a bias voltage.