Non-volatile memory cell with self aligned floating and erase gates, and method of making same

An electrically programmable and erasable memory device comprising:

• a substrate of semiconductor material having a first conductivity type and a surface;
• a trench formed into the surface of the substrate;
• first and second spaced-apart regions formed in the substrate and having a second conductivity type, with a channel region in the substrate there between, wherein the first region is formed under the trench, and the channel region includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate;
• an electrically conductive floating gate at least partially disposed in the trench adjacent to and insulated from the channel region first portion for controlling a conductivity of the channel region first portion;
• an electrically conductive control gate disposed over and insulated from the channel region second portion for controlling a conductivity of the channel region second portion;
• an electrically conductive erase gate disposed adjacent to and insulated from the floating gate;
• and
• a block of conductive material having at least a lower portion thereof disposed in the trench that is electrically connected to the first region and is adjacent to and insulated from the floating gate.