Semiconductor memory devices including recess-type control gate electrodes and methods of fabricating the semiconductor memory devices

A semiconductor memory device, comprising:

• a semiconductor substrate including three or more holes;
• a plurality of control gate electrodes recessed in the semiconductor substrate to fill the plurality of holes;
• a plurality of storage node layers interposed between sidewalls of the control gate electrodes and sidewall portions of the semiconductor substrate exposed from the plurality of holes;
• a plurality of tunneling insulation layers interposed between the storage node layers and the sidewalls portions of the semiconductor substrate;
• a plurality of blocking insulation layers interposed between the storage node layers and the control gate electrodes;
• a continuous first channel region formed around a first region of the sidewall portions of the semiconductor substrate;
• and
• a continuous second channel region formed around a second region of the sidewall portions of the semiconductor substrate;
• wherein adjacent pairs of the tunneling insulation layers contact each other, forming a line of two or more contact regions, to
• separate the sidewall portions of the semiconductor substrate into the first and second channel regions,
• and each of the plurality of control gate electrodes is formed symmetrically about a line connecting the tunneling insulation layers along points of the two or more contact regions.

A semiconductor memory device, comprising:

• a semiconductor substrate including at least one hole;
• a control gate electrode recessed in the semiconductor substrate to fill the at least one hole;
• a storage node layer interposed between a sidewall of the control gate electrode and a sidewall portion of the semiconductor substrate exposed from the at least one hole;
• a tunneling insulation layer interposed between the storage node layer and the sidewall portion of the semiconductor substrate;
• a blocking insulation layer interposed between the storage node layer and the control gate electrode;
• a buried insulation layer interposed between a bottom of the control gate electrode and the semiconductor substrate;
• and
• first and second channel regions formed around the sidewall portion of the semiconductor substrate;
• wherein the tunneling insulation layer extends from the buried insulation layer to a surface of the semiconductor substrate,
• wherein the first and second channel regions are separated from each other via separating insulation layers, and
• wherein the control gate electrode is formed symmetrically about a line connecting the separating insulation layers.