Transistor device having asymmetric embedded strain elements and related manufacturing method

A semiconductor transistor device comprising:

• a layer of semiconductor material;
• a gate structure overlying the layer of semiconductor material, the gate structure comprising a source sidewall and a drain sidewall;
• a first spacer formed on the source sidewall;
• a second spacer formed on the drain sidewall;
• a source region in the layer of semiconductor material, the source region comprising a stress-inducing semiconductor material with a stepped profile having an upper portion that extends under the first spacer, and having a lower portion that is self-aligned with the first spacer;
• and
• a drain region in the layer of semiconductor material, the drain region comprising the stress-inducing semiconductor material with a stepped profile having an upper portion that is self-aligned with the second spacer;
• wherein
• the minimum distance between the stress-inducing semiconductor material of the source region and a projection of the source sidewall into the layer of semiconductor material is less than the minimum distance between the stress-inducing semiconductor material of the drain region and a projection of the drain sidewall into the layer of semiconductor material.