Cross-point diode arrays and methods of manufacturing cross-point diode arrays

A method of forming an array of memory cells, comprising:

• forming a plurality of pillars comprising fabricating a shallow trench isolation structure having array trenches and an oxide in the array trenches, forming a column trench mask, and etching column trenches in the semiconductor material that space apart the columns of the pillars, wherein individual pillars have a semiconductor post formed of a semiconductor material and a sacrificial cap on the semiconductor post;
• forming source regions between columns of the pillars, wherein forming the source regions comprises implanting an N-type implant into the semiconductor material at a bottom of the column trenches;
• forming a plurality of gate lines, wherein individual gate lines extend along a corresponding column of pillars and are spaced apart from corresponding source regions, wherein each gate line surrounds a portion of the semiconductor posts along a column of pillars, and wherein forming the gate lines comprises filling the column trenches with an oxide, etching the oxide in the array trenches and the column trenches to a depth spaced apart from the source regions, depositing a metal into the array trenches and the column trenches such that the metal fills the array trenches but does not fill the column trenches, and spacer etching the metal to a level spaced apart from the sacrificial caps;
• selectively removing the sacrificial caps and thereby forming self-aligned openings that expose a top portion of corresponding semiconductor posts, wherein selectively removing the sacrificial caps comprises etching away the sacrificial caps without photo-patterning a mask with a pattern of openings corresponding to the pattern of the self-aligned openings;
• and
• forming individual drain contacts in the self-aligned openings that are electrically connected to corresponding semiconductor posts.

A method of forming an array of vertical memory cells, comprising:

• forming a plurality of pillars, wherein each pillar has a semiconductor post and a sacrificial cap, and wherein the pillars are arranged in rows spaced apart by a row spacing and columns spaced apart by a column spacing larger than the row spacing;
• forming source regions at a proximal region of the semiconductor posts;
• forming gate lines that surround an intermediate section of the semiconductor posts;
• selectively removing the sacrificial caps comprising etching away the sacrificial caps without forming a mask corresponding to a pattern of the sacrificial caps, thereby forming self-aligned openings over a distal portion of each of the semiconductor posts;
• and
• forming drain contacts in the self-aligned openings that are electrically connected to corresponding semiconductor posts.