On-chip heater and methods for fabrication thereof and use thereof
AssigneeInternational Business Machines Corporation
InventorsEthan H. Cannon, Alvin W. Strong
Life of this patent
Estimating the term…
Abstract
An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.
Claims16
A semiconductor structure comprising:
- at least one trench isolation region located within a semiconductor substrate, the at least one trench isolation region comprised of a single dielectric material selected from the group consisting of oxides, nitrides and oxynitrides;
- at least one heater comprised of a resistive polysilicon material located embedded within the at least one trench isolation region, wherein a unitary and U-shaped remaining portion of the single dielectric material of the at least one trench isolation region is present in direct contact with a base and sidewalls of the at least one heater, wherein an upper surface of the at least one heater is below an upper surface of the semiconductor substrate;
- and
- a capping layer of a dielectric material on the upper surface of the at least one heater, wherein an upper surface of the capping layer is coplanar with an upper surface of the semiconductor substrate.
A method for neutralizing a charged semiconductor structure comprising:
- forming at least one trench isolation region comprised of a single dielectric material selected from the group consisting of oxides, nitrides and oxynitrides within a semiconductor substrate;
- removing a central portion of the at least one trench isolation region;
- forming a heater composed of resistive polysilicon material on a remaining portion of the trench isolation region, wherein a base surface and sidewall surface of the at least one heater is in direct contact with the remaining portion of the trench isolation region;
- exposing a semiconductor structure to ionizing radiation having an energy that provides for generating a trapped charge within the semiconductor structure;
- and
- thermally annealing the trapped charge to neutralize the trapped charge, the thermal annealing being undertaken using the at least one heater located embedded within the at least one trench isolation region within a semiconductor substrate, wherein an upper surface of the at least one heater is below an upper surface of the semiconductor substrate.
A method for neutralizing a charged semiconductor structure comprising:
- exposing a semiconductor structure to ionizing radiation having an energy that provides for generating a trapped charge within the semiconductor structure;
- and
- thermally annealing the trapped charge to neutralize the trapped charge, the thermal annealing being undertaken using at least one heater located embedded within at least one isolation region within a semiconductor substrate within the semiconductor structure, wherein the semiconductor structure further comprises redundant components each of which has a separate heater, wherein a quantity of the redundant components is adequate to perform the thermally annealing with at least one redundant component, while remaining redundant components operate.
Dependencies are inferred from the claim text.