Method for forming fine patterns in semiconductor device
AssigneeHynix Semiconductor Inc.
InventorsSung-Yoon Cho, Chang-Goo Lee
Life of this patent
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Abstract
A method for forming fine patterns in a semiconductor device includes forming a first hard mask layer over an etch target layer, forming first etch mask patterns having negative slopes over the first hard mask layer, thereby forming a resultant structure, forming a first material layer for a second etch mask over the resultant structure, performing a planarization process until the first etch mask patterns are exposed to form second etch mask patterns filled in spaces between the spacers, removing the spacers, and etching the first hard mask layer and the etch target layer using the first etch mask patterns and the second etch mask patterns.
Claims18
A method for forming patterns in a semiconductor device, the method comprising:
- forming a first hard mask layer over an etch target layer;
- forming first etch mask patterns having negative slopes over the first hard mask layer;
- forming spacers on sidewalls of the first etch mask patterns, thereby forming a first resultant structure;
- forming a first material layer over the first resultant structure, thereby forming a second resultant structure;
- performing a planarization process on the second resultant structure until the first etch mask patterns are exposed, thereby forming second etch mask patterns filled in spaces between the spacers;
- removing the spacers;
- and
- etching the first hard mask layer and the etch target layer using the first etch mask patterns and the second etch mask patterns as etch masks.
A method for forming patterns in a semiconductor device, the method comprising:
- forming a first hard mask layer over an etch target layer;
- forming first etch mask patterns having negative slopes over the first hard mask layer;
- forming spacers on sidewalls of the first etch mask patterns;
- forming a first material layer covering the resultant structure including the spacers;
- performing a planarization process on the first material layer until the first etch mask patterns are exposed thereby forming second etch mask patterns;
- removing the spacers;
- etching portions of the first hard mask layer using the first etch mask patterns and the second etch mask patterns as etch masks;
- removing the first etch mask patterns and the second etch mask patterns;
- etching the etch target layer using the first hard mask layer as a mask;
- and
- removing the first hard mask layer.
A method for forming patterns in a semiconductor device, the method comprising:
- forming a first hard mask layer over an etch target layer;
- patterning a portion of the first hard mask layer so that the resulting patterns have positive slopes;
- forming a first material layer over a resultant structure including the resulting patterns;
- performing a planarization process on the first material layer until a surface of the resulting patterns are exposed thereby forming first etch mask patterns having negative slopes;
- depositing a second material layer on a surface of a second resultant structure including the first etch mask patterns;
- forming spacers on sidewalls of the first etch mask patterns;
- forming a third material layer over a third resultant structure including the first etch mask patterns and the spacers;
- performing a planarization process on the third material layer, the first etch mask patterns, and the spacers until the first etch mask patterns are exposed and remain with a predetermined thickness thereby forming second etch mask patterns;
- sequentially etching portions of the first hard mask layer using the first etch mask pattern and the second etch mask pattern as a mask;
- removing the first etch mask pattern and the second etch mask pattern;
- etching the etch target layer using the first hard mask layer as a mask;
- and
- removing the remaining portions of the first hard mask layer.
Dependencies are inferred from the claim text.