ICs with end gates having adjacent electrically connected field poly

A lithography mask set for forming an integrated circuits (IC), comprising:

• a polysilicon (poly) mask, said poly mask including:
• a first active poly gate feature having a line width W1 over an end of a first active area, said first active area framed by a first active area edge, and at least a first adjacent active field poly feature having a line width 0.8W1 to 1.3W1 in a first field region positioned to maintain a gate pitch of said first active poly gate feature, said first adjacent active field poly feature connected to at least one of said first active poly gate feature and another active gate, said first field poly feature having a vertical portion along a gate length direction of said first active poly gate feature and a horizontal portion including a first extension portion along a gate width direction of said first active poly gate feature that extends over said first active area edge, wherein a first minimum spacing (S1) is between said first extension portion and said first active area edge, and
• a second active poly gate feature over an end of a second active area framed by a second active area edge connected to a second field poly feature in a second field region having a vertical portion parallel to a gate length direction of said second active poly gate and a horizontal portion including a second extension portion that extends over said second active area edge along a gate width direction of said second active poly gate feature, and a dummy field poly feature interposed between said second active poly gate feature and said second field poly feature, wherein a second minimum spacing (S2) is between said second extension portion and said second active area edge,
• wherein S1≧1.25S2.

An integrated circuit (IC), comprising:

• a substrate having a topside semiconductor surface including at least one active area and at least one field region;
• a plurality of MOS transistors formed with said active area, comprising:
• a first gate portion comprising a first active poly gate feature having a line width W1 over an end of a first active area, said first active area framed by a first active area edge, and at least a first adjacent active field poly feature having a line width 0.8W1 to 1.3W1 in a first field region positioned to maintain a gate pitch of said first active poly gate feature, said first adjacent active field poly feature electrically connected to at least one of said first active poly gate feature and another active gate feature, said first adjacent active field poly feature having a vertical portion along a gate length direction of said first active poly gate feature and a horizontal portion including a first extension portion along a gate width direction of said first active poly gate feature that extends over said first active area edge, wherein a first minimum spacing (S1) is between said first extension portion and said first active area edge;
• a second gate portion comprising a second active poly gate feature over an end of a second active area framed by a second active area edge electrically connected to a second field poly feature in a second field region having a vertical portion parallel to a gate length direction of said second active poly gate and a horizontal portion including a second extension portion that extends over said second active area edge along a gate width direction of said second active poly gate feature, and a dummy field poly feature interposed between said second active poly gate feature and said second field poly feature, wherein a second minimum spacing (S2) is between said second extension portion and said second active area edge,
• wherein S1≧1.25 S2, and
• a source and a drain region on opposing sides of said first active poly gate feature and said second active poly gate feature.