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US 8,136,070 B2Granted
Shallow trench isolation dummy pattern and layout method using the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKelvin Yih-Yuh Doong, Chin-Chiu Hsia
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Abstract
A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed.
Claims13
A semiconductor device, comprising:
- a substrate having a shallow trench isolation area;
- at least one dummy active layer within the shallow trench isolation area, the top surface of the dummy active layer substantially level with that of the shallow trench isolation area;
- and
- at least one first dummy polysilicon layer formed on the shallow trench isolation area and outside the underlying dummy active layer.
1 more element
Dependencies are inferred from the claim text.