Method and apparatus to reduce footprint of ESD protection within an integrated circuit

A method of discharging an electrostatic discharge (“ESD”) event on an input pin of an input/output (“I/O”) circuit of an integrated circuit (“IC”) comprising:

• applying a high voltage associated with the ESD event to the input pin;
• coupling the high voltage to an ESD N-well bias circuit of the IC;
• producing an ESD N-well bias voltage;
• coupling the ESD N-well bias voltage to an N-well of a PMOS single-ended driver having a PMOS FET with a first breakdown voltage between a first PMOS drain and the N-well, the first PMOS drain being directly connected to the input pin;
• coupling the high voltage to a first NMOS drain of an NMOS FET of an NMOS single-ended driver having a second breakdown voltage between the first NMOS drain and a substrate of the IC less than the first breakdown voltage;
• and
• discharging the ESD event through the first NMOS drain to the substrate.

An integrated circuit (“IC”) having an input/output (“I/O”) circuit comprising:

• an input pin;
• a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) having a first NMOS source and a first NMOS drain incorporating a silicide block electrically coupling the first NMOS FET to the input pin;
• a first P-channel metal-oxide semiconductor (“PMOS”) FET having a first PMOS drain directly connected to the input pin, a first PMOS source electrically coupled to a positive voltage supply, and a PMOS N-well electrically coupled to the input pin through an electro-static discharge (“ESD”) well bias circuit providing an ESD well bias voltage;
• an NMOS low-voltage differential signal (“LVDS”) driver having a second drain of a second NMOS FET directly connected to the input pin, the second NMOS FET fabricated within a first P-tap guard ring electrically coupled to ground, an N-well guard ring coupled to the ESD well bias voltage surrounding the first P-tap guard ring, and a second source of the second NMOS FET being electrically coupled to a third drain of a third NMOS FET fabricated within a second P-tap guard ring electrically coupled to ground and surrounding the third NMOS FET;
• and
• a PMOS LVDS driver having a second PMOS FET with a second PMOS drain directly connected to the input pin and having a second PMOS N-well coupled to the ESD well bias voltage.