Programmable frequency divider

A method comprising:

• a register receiving and storing a divisor by which an input clock signal is to be divided to produce an output clock signal, wherein a least significant bit (LSB) of the divisor indicates whether the divisor is even or odd;
• a counter decrementing a counter value from an initial value derived from the divisor, wherein the decrementing is responsive to a first edge of the input clock signal;
• a detector detecting that the counter value is equivalent to one of a first trigger or a second trigger value depending on whether the divisor is even or odd, respectively;
• asserting one of a first trigger signal or a second trigger signal responsive to detecting the counter value is equivalent to one of the first or second trigger values, respectively;
• and
• toggling an output clock signal responsive to the asserting.

An integrated circuit comprising:

• a clock generation unit configured to generate a first clock signal responsive to a reference clock signal;
• and
• a clock divider coupled to receive the first clock signal and further configured to produce an output clock signal by dividing the input clock signal, wherein the clock divider is coupled to receive an N-bit divisor representing an integer value by which a frequency of the first clock signal is to be divided, wherein the clock divider comprises:
• a counter coupled to receive a counter value derived from the divisor, wherein the counter is configured to decrement the counter value responsive to a first edge of the first clock signal;
• a detector configured to detect when the counter value is equal to a trigger value, wherein the trigger value is dependent on a least significant one of the N bits of the divisor and, responsive to detecting that the counter value is equal to the trigger value, assert a first or second trigger signal depending on the least significant one of the N bits, and further configured to reload the counter with the counter value responsive to detecting the trigger value, and further configured to assert a toggle signal responsive to detecting the trigger value;
• and
• an output unit configured to toggle an output clock signal responsive to receiving the toggle signal.

A system comprising:

• a power supply;
• and
• an integrated circuit (IC) coupled to receive power from the power supply, wherein the IC includes a clock divider configured to generate a divided clock signal responsive to an input clock signal, wherein the clock divider is programmable with a divisor having N bits that represent an integer value by which a frequency of the input clock signal is to be divided to produce the divided clock signal, wherein the clock divider comprises:
• a counter unit that is initialized to an initial counter value corresponding to the divisor and which is configured to decrement the counter value responsive to the input clock signal;
• and
• wherein the clock divider is configured to detect that the counter value is equal to a trigger value that depends on whether the integer value is even or odd, and wherein the clock divider is configured to toggle the divided clock signal responsive to detecting that the counter value is equal to the trigger value.