Triggered silicon controlled rectifier for RF ESD protection
AssigneesGlobalfoundries Singapore Pte. Ltd., Agilent Technologies, Inc.
InventorsIndrajit Manna, Lo Keng Foo, Tan Pee Ya, Raymond Filippi
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Abstract
An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
Claims32
A silicon controlled rectifier formed on a substrate comprising:
- a first well region lightly doped with impurities of a first conductivity type formed on said substrate;
- a second well region formed within said first well region and lightly doped with impurities of a second conductivity type;
- a first diffusion region formed within said second well and heavily doped with the impurities of the first conductivity type;
- a second diffusion region formed within said first well region and heavily doped with impurities of the second conductivity type;
- a junction between the first well region and the second well region;
- and
- a heavily doped polycrystalline layer formed at the surface of said substrate and placed between the first and second diffusion regions and astride the junction of the first well region and the second well region to form a bounding component to prevent silicide formation at junctions of the first diffusion region and the second well region, the first well region and the second region, and the second diffusion region and the first well region during fabrication of said silicon controlled rectifier.
An ESD protection circuit formed at an input/output of an integrated circuit to protect said integrated circuit from damage caused by an ESD event, said ESD protection circuit comprising:
- a polycrystalline silicon bounded SCR having a first gate and a second gate and the polycrystalline silicon bounded SCR connected between a signal input/output interface of said integrated circuit and a power supply connection of said integrated circuit, said polycrystalline silicon bounded SCR comprising:
- a first well region lightly doped with impurities of a first conductivity type formed on said substrate and connected to said power supply connection,
- a second well region formed within said first well region and lightly doped with impurities of a second conductivity type,
- a first diffusion region formed within said second well, heavily doped with the impurities of the first conductivity type, and connected to said signal input/output interface,
- a second diffusion region formed within said first well region, heavily doped with impurities of the second conductivity type, and connected to said power supply connection,
- a junction between the first well region and the second well region,
- a first heavily doped polycrystalline layer formed at the surface of said substrate and placed between the first and second diffusion regions and astride the junction of the first well region and the second well region to form a bounding component to prevent silicide formation at junctions of the first diffusion region and the second well region, the first well region and the second region, and the second diffusion region and the first well region during fabrication of said silicon controlled rectifier;
- and
- a biasing circuit connected to said polycrystalline silicon hounded SCR to bias said polycrystalline silicon bounded SCR to turn on more rapidly during said ESD event.
An ESD protection circuit formed at an input/output of an integrated circuit to protect said integrated circuit from damage caused by an ESD event, said ESD protection circuit comprising:
- a shallow trench isolation bounded SCR having an anode connection, a first gate, and a second gate, and the shallow trench isolation bounded SCR connected between a signal input/output interface of said integrated circuit and a power supply connection of said integrated circuit;
- at least one diode formed on a substrate and connected between said signal input/output interface and the anode connection of said shallow trench isolation bounded SCR to increase a holding voltage for said shallow trench isolation bounded SCR when said shallow trench isolation bounded SCR is turned on;
- and
- a biasing circuit connected to said shallow trench isolation hounded SCR to bias said shallow trench isolation bounded SCR to turn on more rapidly during said ESD event.
Dependencies are inferred from the claim text.