Capacitorless one-transistor semiconductor memory device having improved data retention abilities and operation characteristics
AssigneeSamsung Electronics Co., Ltd.
InventorsNam-Kyun Tak, Ki-Whan Song
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Abstract
A capacitorless one transistor (1T) semiconductor device whose data storage abilities are increased and leakage current is reduced is provided. The capacitor-less 1T semiconductor device includes a buried insulating layer formed on a substrate, an active region formed on the buried insulating layer and including a source region, a drain region and a floating body formed between the source region and the drain region, and a gate pattern formed on the floating body, wherein the floating body includes a main floating body having the same top surface height as one of the source region and the drain region, and a first upper floating body formed between the main floating body and the gate pattern.
Claims18
A capacitorless one-transistor (1T) semiconductor device, comprising:
- a buried insulating layer on a substrate;
- an active region on the buried insulating layer, the active region including a source region, a drain region, and a floating body between the source region and the drain region;
- and
- a gate pattern on the floating body,
- wherein the floating body includes a main floating body and a first upper floating body directly contacting and being integral with each other, top surfaces of the main floating body and at least one of the source region and the drain region facing away from the buried insulating layer being substantially coplanar, and the first upper floating body being between the main floating body and the gate pattern, and
- wherein the floating body further includes a flank floating body, the flank floating body having a top surface at a lower height than a top surface of the upper floating body, the flank floating body being positioned between the main floating body and at least one of the source and drain regions.
A capacitor-less one-transistor (1T) semiconductor device, comprising:
- a buried insulating layer on a substrate;
- an active region on the buried insulating layer, the active region including a source region, a drain region, and a floating body between the source region and the drain region;
- and
- a gate pattern on the floating body,
- wherein the floating body includes a main floating body and a charge storage pattern, side surfaces of the main floating body directly contacting the gate pattern, top surfaces of the main floating body and at least one of the source region and the drain region facing away from the buried insulating layer being substantially coplanar, and the charge storage pattern being between the main floating body and the gate pattern,
- wherein the charge storage pattern includes a charge storage insulating layer on the main floating body and a charge storage unit on the charge storage insulating layer, and
- wherein the floating body includes a flank floating body having a top surface at a lower height than the charge storage pattern and adjacent to at least one of the source and drain regions, the flank floating body having no overlaps with the gate electrode.
Dependencies are inferred from the claim text.