Nonvolatile semiconductor memory
AssigneeKabushiki Kaisha Toshiba
InventorYuji Takeuchi
Life of this patent
Estimating the term…
Abstract
A nonvolatile semiconductor memory fabrication method including forming a first insulating film and a floating gate electrode material on a semiconductor substrate; forming a gate insulating film and a floating gate electrode by etching the first insulating film and the floating gate electrode material, respectively, and forming a groove for an element isolation region by etching the semiconductor substrate; and forming an element region and the element isolation region by burying a second insulating film in the groove and planarizing the second insulating film.
Claims15
A nonvolatile semiconductor memory, comprising:
- a floating gate electrode formed on a gate insulating film on an element region isolated by element isolation regions in a first direction on a semiconductor substrate;
- an inter-gate insulating film which is in contact with a portion from an upper surface to a part of a side surface of said floating gate electrode;
- and
- a control gate electrode formed on said floating gate electrode via said inter-gate insulating film,
- wherein the upper surface of said floating gate electrode has a round-arched shape in the first direction.
The memory according to clam 1, wherein an upper portion of the side surface of said floating gate electrode that is in contact with the said inter-gate insulating film has a shape, in which toward the upper surface of said floating gate electrode, an inclination angle of the side surface of said floating gate electrode to a direction perpendicular to a surface of said semiconductor substrate increases.
A nonvolatile semiconductor memory, comprising:
- element isolation regions disposed in a semiconductor substrate;
- a floating gate electrode formed on a gate insulating film on an element region isolated by said element isolation regions in a first direction;
- an inter-gate insulating film contacting with said floating gate electrode above an upper surface of said element isolation region;
- and
- a control gate electrode formed on said floating gate electrode via said inter-gate insulating film, wherein an upper surface of said floating gate electrode has a round-arched shape in the first direction.
Dependencies are inferred from the claim text.