US 8,133,814 B1Granted

Etch methods for semiconductor device fabrication

AssigneeGlobalfoundries Inc.

InventorsSteffen Laufer, Gunter Grasshoff

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Abstract

Methods are provided for fabricating a semiconductor device. One embodiment includes forming an insulator layer overlying a semiconductor substrate and depositing a layer of polycrystalline silicon overlying the insulator layer. Conductivity determining impurity ions are implanted into at least an upper portion of the layer of polycrystalline silicon. At least the upper portion of the layer of polycrystalline silicon is etched using a first anisotropic etch chemistry to expose an edge portion of the upper portion. An oxide barrier is formed on the edge portion and a further portion of the layer of polycrystalline silicon is etched using the first anisotropic etch chemistry. Then a final portion of the layer of polycrystalline silicon is etched using a second anisotropic etch chemistry.

Claims12

Dependent claims

A method for fabricating a semiconductor device comprising:

forming an insulator layer overlying a semiconductor substrate;
depositing a layer of polycrystalline silicon overlying the insulator layer;
implanting conductivity determining impurity ions into at least an upper portion of the layer of polycrystalline silicon;
etching through the at least upper portion of the layer of polycrystalline silicon using a first anisotropic etch chemistry to expose an edge portion of the at least upper portion of the layer of polycrystalline silicon;
forming an oxide barrier on the edge portion;
etching a further portion of the layer of polycrystalline silicon using the first anisotropic etch chemistry;
and
etching a final portion of the layer of polycrystalline silicon using a second anisotropic etch chemistry;
wherein etching using the first anisotropic etch chemistry comprises etching using an etch chemistry selected to etch the insulator layer and polycrystalline silicon at comparable rates and wherein etching using the second anisotropic etch chemistry comprises etching using an etch chemistry selected to etch polycrystalline silicon at a substantially higher etch rate than the etch rate of the insulator layer;
wherein etching using the first anisotropic etch chemistry comprises etching using an etch chemistry comprising CF4 and wherein etching using the second anisotropic etch chemistry comprises etching using an etch chemistry comprising a halogen and oxygen.

7 more elements

A method for fabricating a semiconductor device comprising:

forming a gate insulator layer overlying a semiconductor substrate;
depositing a layer of polycrystalline silicon overlying the gate insulator layer;
implanting conductivity determining ions into at least an upper portion of the layer of polycrystalline silicon;
forming a patterned masking layer overlying the layer of polycrystalline silicon;
reactive ion etching through the at least an upper portion of the layer of polycrystalline silicon using a non-selective etch chemistry and using the patterned masking layer as an etch mask and leaving an unetched portion of the layer of polycrystalline silicon;
subjecting the unetched portion of the layer of polycrystalline silicon to an oxygen plasma to form an oxide barrier layer on the unetched portion;
reactive ion etching through the oxide barrier layer and a further portion of the layer of polycrystalline silicon using a non-selective etch chemistry and leaving a remaining portion of the layer of polycrystalline silicon;
reactive ion etching the remaining portion of the layer of polycrystalline silicon and stopping on the gate insulator layer to form a gate electrode using a selective etch chemistry;
and
implanting conductivity determining ions into the semiconductor substrate to form source and drain regions in alignment with the gate electrode.

7 more elements

Dependencies are inferred from the claim text.