Layout method of semiconductor device with junction diode for preventing damage due to plasma charge

A layout method for forming a unit layout pattern, the method comprising:

• forming an active layer so as to form first through third active regions in the unit layout pattern, each of the first through third active regions extending along a first direction and having a width in a second direction perpendicular to the first direction;
• forming a gate layer so as to form a first and second gate regions on the first and second active regions, wherein the first and second gate regions are electrically connected to each other;
• forming, within a second conductive type well region, and in the first active region, a first conductive type active layer;
• forming a second conductive type active layer in the second active region;
• and
• forming a second conductive type active layer in the third active region so as to form a junction diode, such that the second conductive type active layer in the third active region is located between the first and second active regions within the widths in the second direction of the first and second active regions.