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AssigneeInternational Business Machines Corporation
InventorsSivananda Kanakasabapathy, Hemanth Jagannathan
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A method is provided for fabricating a semiconductor device having implanted source/drain regions and a gate region, the gate region having been masked by the gate hardmask during source/drain implantation, the gate region having a polysilicon gate layered on a metal layered on a high-K dielectric layer. The gate region and the source/drain regions may be covered with a self planarizing spin on film. The film may be blanket etched back to uncover the gate hardmask while maintaining an etched back self planarizing spin on film on the implanted source/drain regions. The gate hardmask may be etched back while the etched back film remains in place to protect the implanted source/drain regions. The gate region may be low energy implanted to lower sheet resistance of the polysilicon layer. The etched back film may be then removed.
A method of fabricating a semiconductor device having implanted source/drain regions and a gate region, the gate region having been masked by the gate hardmask during a source/drain implantation, the gate region having a polysilicon gate layer layered on a metal layer that is layer on a high-K dielectric layer, the method comprising:
A method of fabricating a semiconductor device having implanted source/drain regions and a gate region, the gate region having been masked by the gate hardmask during source/drain implantation, the gate region having a polysilicon gate layer layered on a metal layer that is layered on a high-K dielectric layer, the method comprising:
Dependencies are inferred from the claim text.