Semiconductor device and electronic apparatus using the same
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsKiyoshi Kato, Takeshi Osada
Life of this patent
Estimating the term…
Abstract
A semiconductor device with high function, multifunction and high added value. The semiconductor device includes a PLL circuit that is provided over a substrate and outputs a signal with a correct frequency. By providing such a PLL circuit over the substrate, a semiconductor device with high function, multifunction and high added value can be achieved.
Claims88
A semiconductor device comprising:
- a low potential power supply;
- a high potential power supply;
- and
- a voltage controlled oscillator, the voltage controlled oscillator comprising:
- a first circuit comprising a first N-type transistor and a first P-type transistor;
- a second circuit comprising a second N-type transistor;
- a third circuit comprising a second P-type transistor;
- and
- a fourth circuit comprising a third N-type transistor and a third P-type transistor,
- wherein one of a source and a drain of the first N-type transistor is electrically connected to one of a source and a drain of the first P-type transistor,
- wherein the other of the source and the drain of the first N-type transistor is electrically connected to one of a source and a drain of the second N-type transistor,
- wherein the other of the source and the drain of the first P-type transistor is electrically connected to one of a source and a drain of the second P-type transistor,
- wherein one of a source and a drain of the third N-type transistor is electrically connected to one of a source and a drain of the third P-type transistor,
- wherein the other of the source and the drain of the second N-type transistor and the other of the source and the drain of the third N-type transistor are electrically connected to the low potential power supply,
- wherein the other of the source and the drain of the second P-type transistor and the other of the source and the drain of the third P-type transistor are electrically connected to the high potential power supply,
- wherein a threshold voltage of the second N-type transistor is lower than that of the first N-type transistor,
- wherein a threshold voltage of the third N-type transistor is lower than that of the first N-type transistor,
- wherein a first signal is inputted to a gate of the second N-type transistor and a gate of the third N-type transistor, and
- wherein a second signal is outputted from the one of the source and the drain of the first N-type transistor and the one of the source and the drain of the first P-type transistor.
A semiconductor device comprising:
- a low potential power supply;
- a high potential power supply;
- and
- a voltage controlled oscillator, the voltage controlled oscillator comprising:
- a first circuit comprising a first N-type transistor and a P-type transistor;
- and
- a second circuit comprising a second N-type transistor;
- wherein one of a source and a drain of the first N-type transistor is electrically connected to one of a source and a drain of the P-type transistor,
- wherein the other of the source and the drain of the first N-type transistor is electrically connected to one of a source and a drain of the second N-type transistor,
- wherein the other of the source and the drain of the second N-type transistor is electrically connected to the low potential power supply,
- wherein the other of the source and the drain of the P-type transistor is electrically connected to the high potential power supply,
- wherein a threshold voltage of the second N-type transistor is lower than that of the first N-type transistor,
- wherein a first signal is inputted to a gate of the second N-type transistor, and
- wherein a second signal is outputted from the one of the source and the drain of the first N-type transistor and the one of the source and the drain of the P- type transistor.
A semiconductor device comprising:
- a low potential power supply;
- a high potential power supply;
- and
- a voltage controlled oscillator, the voltage controlled oscillator comprising:
- a first circuit comprising a first N-type transistor and a first P-type transistor;
- a second circuit comprising a second N-type transistor;
- a third circuit comprising a second P-type transistor;
- and
- a fourth circuit comprising a third N-type transistor and a third P-type transistor;
- wherein one of a source and a drain of the first N-type transistor is electrically connected to one of a source and a drain of the first P-type transistor,
- wherein the other of the source and the drain of the first N-type transistor is electrically connected to one of a source and a drain of the second N-type transistor,
- wherein the other of the source and the drain of the first P-type transistor is electrically connected to one of a source and a drain of the second P-type transistor,
- wherein one of a source and a drain of the third N-type transistor is electrically connected to one of a source and a drain of the third P-type transistor,
- wherein the other of the source and the drain of the second N-type transistor and the other of the source and the drain of the third N-type transistor are electrically connected to the low potential power supply,
- wherein the other of the source and the drain of the second P-type transistor and the other of the source and the drain of the third P-type transistor are electrically connected to the high potential power supply,
- wherein a threshold voltage of the second P-type transistor is higher than that of the first P-type transistor,
- wherein a threshold voltage of the third P-type transistor is higher than that of the first P-type transistor,
- wherein a first signal is inputted to a gate of the second P-type transistor and a gate of the third P-type transistor, and
- wherein a second signal is outputted from the one of the source and the drain of the first N-type transistor and the one of the source and the drain of the first P- type transistor.
A semiconductor device comprising:
- a low potential power supply;
- a high potential power supply;
- and
- a voltage controlled oscillator, the voltage controlled oscillator comprising:
- a first circuit comprising an N-type transistor and a first P-type transistor;
- and
- a second circuit comprising a second P-type transistor,
- wherein one of a source and a drain of the first P-type transistor is electrically connected to one of a source and a drain of the N-type transistor,
- wherein the other of the source and the drain of the first P-type transistor is electrically connected to one of a source and a drain of the second P-type transistor,
- wherein the other of the source and the drain of the second P-type transistor is electrically connected to the high potential power supply,
- wherein the other of the source and the drain of the N-type transistor is electrically connected to the low potential power supply,
- wherein a threshold voltage of the second P-type transistor is higher than that of the first P-type transistor,
- wherein a first signal is inputted to a gate of the second P-type transistor, and
- wherein a second signal is outputted from the one of the source and the drain of the N-type transistor and the one of the source and the drain of the first P-type transistor.
A semiconductor device comprising:
- a low potential power supply;
- a high potential power supply;
- and
- a voltage controlled oscillator, the voltage controlled oscillator comprising:
- a first circuit comprising a first N-type transistor and a first P-type transistor;
- a second circuit comprising a second N-type transistor;
- a third circuit comprising a second P-type transistor;
- and
- a fourth circuit comprising a third N-type transistor and a third P-type transistor,
- wherein one of a source and a drain of the first N-type transistor is electrically connected to one of a source and a drain of the first P-type transistor,
- wherein the other of the source and the drain of the first N-type transistor is electrically connected to one of a source and a drain of the second N-type transistor,
- wherein the other of the source and the drain of the first P-type transistor is electrically connected to one of a source and a drain of the second P-type transistor,
- wherein one of a source and a drain of the third N-type transistor is electrically connected to one of a source and a drain of the third P-type transistor,
- wherein the other of the source and the drain of the second N-type transistor and the other of the source and the drain of the third N-type transistor are electrically connected to the low potential power supply,
- wherein the other of the source and the drain of the second P-type transistor and the other of the source and the drain of the third P-type transistor are electrically connected to the high potential power supply,
- wherein a channel length of the second N-type transistor is shorter than that of the first N-type transistor,
- wherein a channel length of the third N-type transistor is shorter than that of the first N-type transistor,
- wherein a first signal is inputted to a gate of the second N-type transistor and a gate of the third N-type transistor, and
- wherein a second signal is outputted from the one of the source and the drain of the first N-type transistor and the one of the source and the drain of the first P- type transistor.
The semiconductor device according to 45, wherein the semiconductor device is incorporated into an electronic apparatus selected from the group consisting of a mobile phone, a PDA, an electronic notebook, a portable game machine, a TV, a display, a digital camera, a digital video camera, a car audio set, a home game machine, and IC card.
A semiconductor device comprising:
- a low potential power supply;
- a high potential power supply;
- and
- a voltage controlled oscillator, the voltage controlled oscillator comprising:
- a first circuit comprising a first N-type transistor and a P-type transistor;
- and
- a second circuit comprising a second N-type transistor;
- wherein one of a source and a drain of the first N-type transistor is electrically connected to one of a source and a drain of the P-type transistor,
- wherein the other of the source and the drain of the first N-type transistor is electrically connected to one of a source and a drain of the second N-type transistor,
- wherein the other of the source and the drain of the second N-type transistor is electrically connected to the low potential power supply,
- wherein the other of the source and the drain of the P-type transistor is electrically connected to the high potential power supply,
- wherein a channel length of the second N-type transistor is shorter than that of the first N-type transistor,
- wherein a first signal is inputted to a gate of the second N-type transistor, and
- wherein a second signal is outputted from the one of the source and the drain of the first N-type transistor and the one of the source and the drain of the P-type transistor.
A semiconductor device comprising:
- a low potential power supply;
- a high potential power supply;
- and
- a voltage controlled oscillator, the voltage controlled oscillator comprising:
- a first circuit comprising a first N-type transistor and a first P-type transistor;
- a second circuit comprising a second N-type transistor;
- a third circuit comprising a second P-type transistor;
- and
- a fourth circuit comprising a third N-type transistor and a third P-type transistor;
- wherein one of a source and a drain of the first N-type transistor is electrically connected to one of a source and a drain of the first P-type transistor,
- wherein the other of the source and the drain of the first N-type transistor is electrically connected to one of a source and a drain of the second N-type transistor,
- wherein the other of the source and the drain of the first P-type transistor is electrically connected to one of a source and a drain of the second P-type transistor,
- wherein one of a source and a drain of the third N-type transistor is electrically connected to one of a source and a drain of the third P-type transistor,
- wherein the other of the source and the drain of the second N-type transistor and the other of the source and the drain of the third N-type transistor are electrically connected to the low potential power supply,
- wherein the other of the source and the drain of the second P-type transistor and the other of the source and the drain of the third P-type transistor are electrically connected to the high potential power supply,
- wherein a channel length of the second P-type transistors is shorter than that of the first P-type transistor,
- wherein a channel length of the third P-type transistor is shorter than that of the first P-type transistor,
- wherein a first signal is inputted to a gate of the second P-type transistor and a gate of the third P-type transistor, and
- wherein a second signal is outputted from the one of the source and the drain of the first N-type transistor and the one of the source and the drain of the first P-type transistor.
A semiconductor device comprising:
- a low potential power supply;
- a high potential power supply;
- and
- a voltage controlled oscillator, the voltage controlled oscillator comprising:
- a first circuit comprising an N-type transistor and a first P-type transistor;
- and
- a second circuit comprising a second P-type transistor,
- wherein one of a source and a drain of the first P-type transistor is electrically connected to one of a source and a drain of the N-type transistor,
- wherein the other of the source and the drain of the first P-type transistor is electrically connected to one of a source and a drain of the second P-type transistor,
- wherein the other of the source and the drain of the second P-type transistor is electrically connected to the high potential power supply,
- wherein the other of the source and the drain of the N-type transistor is electrically connected to the low potential power supply,
- wherein a channel length of the second P-type transistor is shorter than that of the first P-type transistor,
- wherein a first signal is inputted to a gate of the second P-type transistor, and
- wherein a second signal is outputted from the one of the source and the drain of the N-type transistor and the one of the source and the drain of the first P-type transistor.
Dependencies are inferred from the claim text.