Low power radio frequency divider

A phase-locked loop that generates an output signal of a desired frequency, comprising:

• a phase frequency detector, charge pump and loop filter that generate a control voltage;
• a voltage controlled oscillator that generates a signal whose frequency depends on the control voltage;
• and
• a multi-modulus divider (MMD) circuit that divides the signal that is output from the voltage controlled oscillator, wherein the MMD circuit comprises a cascade of multiple divide-by-2-or-3 cells that divides an input clock signal to produce a pulse signal, and wherein the MMD circuit further comprises a pulse stretching circuit that extends the duration of the pulse signal, thereby outputting an output clock signal, wherein the pulse stretching circuit comprises an RS-latch;
• wherein the cascade of divide-by-2-or-3 cells and the pulse stretching circuit are implemented using full-swing complementary metal-oxide-semiconductor (CMOS) circuits;
• wherein the MMD circuit is configured for an operating frequency of at least 4 GHz;
• and
• wherein the cascade of divide-by-2-or-3 cells and the pulse stretching circuit are organized so that there are no more than two gate delays between a rising edge of the input clock signal and a rising edge of the output clock signal.

A multi-modulus divider (MMD) circuit configured for operation at high frequencies, comprising:

• a clock input that receives an input clock signal;
• a clock output that outputs a divided version of the input clock signal as an output clock signal;
• a cascade of multiple divide-by-2-or-3 cells that divides the input clock signal to produce a pulse signal;
• and
• a pulse stretching circuit that extends the duration of the pulse signal, thereby outputting the output clock signal, wherein the pulse stretching circuit comprises an RS-latch;
• wherein each divide-by-2-or-3 cell is organized so that a critical path of the divide-by-2-or-3 cell comprises a first dynamic flip flop, a second dynamic flip flop, and no more than two logic stages between the first dynamic flip flop and the second dynamic flip flop;
• wherein the MMD circuit is implemented using full-swing complementary metal-oxide-semiconductor (CMOS) circuits;
• wherein the MMD circuit is configured for an operating frequency of at least 4 GHz;
• and
• wherein the cascade of divide-by-2-or-3 cells and the pulse stretching circuit are organized so that there are no more than two gate delays between a rising edge of the input clock signal and a rising edge of the output clock signal.

A phase-locked loop that generates an output signal of a desired frequency, comprising:

• a phase frequency detector that generates a control voltage;
• a voltage controlled oscillator that generates a signal whose frequency depends on the control voltage generated by the phase frequency detector;
• a multi-modulus divider circuit (MMD) that divides the signal that is output from the voltage controlled oscillator;
• a cascade of multiple divide-by-2-or-3 cells that divides an input clock signal to produce a pulse signal;
• and
• a pulse stretching circuit that extends the duration of the pulse signal, thereby outputting an output clock signal, wherein the pulse stretching circuit comprises an RS-latch;
• wherein each divide-by-2-or-3 cell is organized so that a critical path of the divide-by-2-or-3 cell comprises a first dynamic flip flop, a second dynamic flip flop, and no more than two logic stages between the first dynamic flip flop and the second dynamic flip flop;
• wherein the MMD circuit is implemented using full-swing complementary metal-oxide-semiconductor (CMOS) circuits;
• wherein the MMD circuit is configured for an operating frequency of at least 4 GHz;
• and
• wherein the cascade of divide-by-2-or-3 cells and the pulse stretching circuit are organized so that there are no more than two gate delays between a rising edge of the input clock signal and a rising edge of the output clock signal.

A method for using a multi-modulus divider (MMD) circuit configured for operation at high frequencies, comprising:

• a cascade of multiple divide-by-2-or-3 cells dividing an input clock signal to produce a pulse signal;
• and
• a pulse stretching circuit extending the duration of the pulse signal, thereby outputting an output clock signal, wherein the pulse stretching circuit comprises an RS-latch;
• wherein the cascade of divide-by-2-or-3 cells and the pulse stretching circuit are implemented using full-swing complementary metal-oxide-semiconductor (CMOS) circuits;
• wherein the MMD circuit is configured for an operating frequency of at least 4 GHz;
• and
• wherein the cascade of divide-by-2-or-3 cells and the pulse stretching circuit are organized so that there are no more than two gate delays between a rising edge of the input clock signal and a rising edge of the output clock signal.

A multi-modulus divider (MMD) circuit configured for operation at high frequencies, comprising:

• means for dividing an input clock signal to produce a pulse signal;
• and
• means for extending the duration of the pulse signal, thereby outputting an output clock signal, wherein the means for extending the duration of the pulse signal comprises an RS-latch;
• wherein the MMD circuit is implemented using full-swing complementary metal-oxide-semiconductor (CMOS) circuits;
• wherein the MMD circuit is configured for an operating frequency of at least 4 GHz;
• and
• wherein the means for dividing an input clock signal and the means for extending the duration of the pulse signal are organized so that there are no more than two gate delays between a rising edge of the input clock signal and a rising edge of the output clock signal.