Method of designing semiconductor device including density verification
AssigneeFujitsu Semiconductor Limited
InventorDai Kanai
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Abstract
A method of designing a semiconductor device includes density verification of layout data of the semiconductor device at a macro level. The method includes disposing virtual patterns each including a predetermined step width on a circumference of a verification frame; and moving the verification frame outside which the virtual patterns are disposed sequentially by the predetermined step width and performing the density verification of the layout data of the semiconductor device.
Claims16
A method of designing a semiconductor device including density verification of layout data of the semiconductor device at a macro level, comprising:
- disposing virtual patterns each including a predetermined step width close to a circumference of a verification frame using a processing apparatus;
- and
- moving said verification frame outside which said virtual patterns are disposed sequentially by said predetermined step width and performing the density verification of the layout data of said semiconductor device.
A computer readable storage non-transitory medium that stores a layout data verification program of a semiconductor device for making a computer to execute:
- disposing virtual patterns each including a predetermined step width on a circumference of a verification frame;
- and
- moving said verification frame outside which said virtual patterns are disposed sequentially by said predetermined step width and performing the density verification of the layout data of said semiconductor device.
Dependencies are inferred from the claim text.