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US 8,076,753 B2Granted
Semiconductor device and method of manufacturing the same
AssigneeSpansion LLC
InventorKoji Shimbayashi
Life of this patent
Estimating the term…
Abstract
In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are connected, and the N-type diffusion layer of the first MOS device and the gate layer of the second MOS device are connected, and thereby a first capacitive element is composed.
Claims28
A semiconductor device comprising:
- a first MOS device comprising impurities that are formed on a surface of a P-type substrate provided as a base, the P-type substrate including a region located beneath the gate of the first MOS device that is free of added impurities for controlling a threshold voltage wherein the first MOS device has a characteristic that is similar to that of a depletion mode MOS device;
- a second MOS device comprising impurities that are formed on a surface of the P-type substrate provided as a base wherein the impurities that are formed on the surface of the P-type substrate form a well layer that is formed immediately below the gate layer of the second MOS device, wherein the P-type substrate includes a region located beneath the gate of the second MOS device that is free of added impurities in addition to the impurities formed on the surface of the p-type substrate for controlling a threshold voltage wherein the second MOS device has a characteristic that is similar to that of a depletion mode MOS device;
- and
- a third MOS device that is isolated from the first MOS device and the second MOS device by a channel stop region comprising a well layer that is formed below an STI region that has a top surface that is coplanar with said substrate and that extends into second and third well layers wherein the entire channel stop region lies between the second MOS device and the third MOS device,
- wherein the first MOS device and the second MOS device, each have an N-type diffusion region on the surface of the P-type substrate which straddles their respective gate layers,
- wherein the first MOS device and the second MOS device constitute a first capacitive element through the connection of a gate layer and an N-type diffusion layer of the first MOS device to an N-type diffusion layer and a gate layer of the second MOS device, respectively.
3 more elements
A computing device comprising:
- a processor;
- an input component;
- an output component;
- a memory comprising:
- a volatile memory;
- and
- a non-volatile memory comprising:
- a first MOS device comprising impurities that are formed on a surface of a P-type substrate provided as a base, the P-type substrate including includes a region located beneath the gate of the first MOS device that is free of added impurities wherein the first MOS device has a characteristic with depletion mode features;
- a second MOS device comprising impurities that are formed on a surface of the P-type substrate provided as a base wherein the impurities that are formed on the surface of the P-type substrate form a well layer that is formed immediately below the gate layer of the second MOS device, wherein the P-type substrate includes a region located beneath the gate of the second MOS device that is free of impurities in addition to the impurities formed on the surface of the p-type substrate wherein the second MOS device has a characteristic with depletion mode features;
- and
- a third MOS device that is isolated from the first MOS device and the second MOS device by a channel stop region comprising a well layer that is formed below an STI region that has a top surface that is coplanar with said substrate and that extends into second and third well layers wherein the entire channel stop region lies between the second MOS device and the third MOS device,
- wherein the first MOS device and the second MOS device, each have an N-type diffusion region on the surface of the P-type substrate which straddles their respective gate layers,
- wherein the first MOS device and the second MOS device constitute a first capacitive element through the connection of a gate layer and an N-type diffusion layer of the first MOS device to an N-type diffusion layer and a gate layer of the second MOS device, respectively.
10 more elements
A wireless communications device, said wireless communications device comprising:
- a non-volatile memory comprising:
- a first MOS device comprising impurities that are formed on a surface of a P-type substrate provided as a base, the P-type substrate including a region located beneath the gate of the first MOS device that is free of added impurities wherein the first MOS device has a characteristic with depletion mode features;
- a second MOS device comprising impurities that are formed on a surface of the P-type substrate provided as a base wherein the impurities that are formed on the surface of the P-type substrate form a well layer that is formed immediately below the gate layer of the second MOS device, wherein the P-type substrate includes a region located beneath the gate of the second MOS device that is free of impurities in addition to the impurities formed on the surface of the p-type substrate wherein the second MOS device has a characteristic with depletion mode features;
- and
- a third MOS device that is isolated from the first MOS device and the second MOS device by a channel stop region comprising a well layer that is formed below an STI region that has a top surface that is coplanar with said substrate and that extends into second and third well layers wherein the entire channel stop region lies between the second MOS device and the third MOS device,
- wherein the first MOS device and the second MOS device, each have an N-type diffusion region on the surface of the P-type substrate which straddles their respective gate layers,
- wherein the first MOS device and the second MOS device constitute a first capacitive element through the connection of a gate layer and an N-type diffusion layer of the first MOS device to an N-type diffusion layer and a gate layer of the second MOS device, respectively,
- a processor;
- a communications component;
- a transmitter;
- a receiver;
- and
- an antenna connected to the transmitter circuit and the receiver circuit.
10 more elements
A media content player comprising:
- a non-volatile memory that stores one or more media content items, said non-volatile memory comprising:
- a first MOS device comprising impurities that are formed on a surface of a P-type substrate provided as a base, the P-type substrate including a region located beneath the gate of the first MOS device that is free of added impurities wherein the first MOS device has a characteristic with depletion mode features;
- a second MOS device comprising impurities that are formed on a surface of the P-type substrate provided as a base wherein the impurities that are formed on the surface of the P-type substrate form a well layer that is formed immediately below the gate layer of the second MOS device, wherein the P-type substrate includes a region located beneath the gate of the second MOS device that is free of impurities in addition to the impurities formed on the surface of the p-type substrate wherein the second MOS device has a characteristic with depletion mode features;
- and
- a third MOS device that is isolated from the first MOS device and the second MOS device by a channel stop region comprising a well layer that is formed below an STI region that has a top surface that is coplanar with said substrate and that extends into second and third well layers wherein the entire channel stop region lies between the second MOS device and the third MOS device,
- wherein the first MOS device and the second MOS device, each have an N-type diffusion region on the surface of the P-type substrate which straddles their respective gate layers,
- wherein the first MOS device and the second MOS device constitute a first capacitive element through the connection of a gate layer and an N-type diffusion layer of the first MOS device to an N-type diffusion layer and a gate layer of the second MOS device, respectively,
- a user input that enables the selection of one or more of said media item;
- a processor coupled to said user input and said storage component that causes the playback of a selected media item, and
- one or more playback devices for conveying the playback of said media item.
7 more elements
An image acquisition system, comprising:
- an image acquisition component for acquiring image data;
- a storage component for storing image data, said storage component comprising non-volatile memory comprising:
- a first MOS device comprising impurities that are formed on a surface of a P-type substrate provided as a base, the P-type substrate including a region located beneath the gate of the first MOS device that is free of added impurities wherein the first MOS device has a characteristic with depletion mode features;
- a second MOS device comprising impurities that are formed on a surface of the P-type substrate provided as a base wherein the impurities that are formed on the surface of the P-type substrate form a well layer that is formed immediately below the gate layer of the second MOS device, wherein the P-type substrate includes a region located beneath the gate of the second MOS device that is free of impurities in addition to the impurities formed on the surface of the p-type substrate wherein the second MOS device has a characteristic with depletion mode features;
- and
- a third MOS device that is isolated from the first MOS device and the second MOS device by a channel stop region comprising a well layer that is formed below an STI region that has a top surface that is coplanar with said substrate and that extends into second and third well layers wherein the entire channel stop region lies between the second MOS device and the third MOS device,
- wherein the first MOS device and the second MOS device, each have an N-type diffusion region on the surface of the P-type substrate which straddles their respective gate layers,
- wherein the first MOS device and the second MOS device constitute a first capacitive element through the connection of a gate layer and an N-type diffusion layer of the first MOS device to an N-type diffusion layer and a gate layer of the second MOS device, respectively, and
- a display unit for displaying said image data stored in said storage component.
6 more elements
Dependencies are inferred from the claim text.