US 8,076,748 B2Granted

Semiconductor device

AssigneeSeiko Epson Corporation

InventorsTakayuki Saiki, Kazuhiko Okawa

Life of this patent

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Abstract

A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.

Claims5

Dependent claims

A semiconductor device with electrostatic discharge protection, the device comprising:

a substrate including a well;
a first region formed in the substrate, the first region having a first side, a second side, a third side and a fourth side, and a first impurity region having a first conductivity type;
a first electrode group formed on the first region, the first electrode group being formed along the first side;
a second electrode group formed on the first region, the second electrode group being formed along the second side;
a third electrode group formed on the first region, the third electrode group being formed along the third side;
a fourth electrode group formed on the first region, the fourth electrode group being formed along the fourth side;
a second region formed in the substrate, the second region surrounding the first region in a plan view, the second region having a fifth side, a sixth side, a seventh side and an eighth side, and a second impurity region having the first conductivity type that surrounds the first impurity region;
a dielectric film separating the first impurity region and the second impurity region;
a fifth electrode group formed on the second region, the fifth electrode group being formed along the fifth side;
a sixth electrode group formed on the second region, the sixth electrode group being formed along the sixth side;
a seventh electrode group formed on the second region, the seventh electrode group being formed along the seventh side;
and
an eighth electrode group formed on the second region, the eighth electrode group being formed along the eighth side,
wherein the first electrode group faces the fifth electrode group across the first side and the fifth side,
wherein the second electrode group faces the sixth electrode group across the second side and the sixth side,
wherein the third electrode group faces the seventh electrode group across the third side and the seventh side,
wherein the fourth electrode group faces the eighth electrode group across the fourth side and the eighth side,
wherein the first impurity region is formed to overlap each electrode group formed in the first region,
the second impurity region is formed to overlap each electrode group formed in the second region, and
the well is formed in the first region and the second region, a portion of the well separating the first impurity region and the second impurity region acting as a resistor between the first impurity region and the second impurity region to protect the semiconductor device from electro-static discharge.

17 more elements

A semiconductor device with electrostatic discharge protection, the device comprising:

a substrate including a well;
a first region formed in the substrate, the first region having a first side, a second side, a third side and a fourth side, and a first impurity region having a first conductivity type;
a first electrode formed on the first region;
a second electrode formed on the first region;
a third electrode formed on the first region;
a fourth electrode formed on the first region;
a fifth electrode formed on the first region;
a sixth electrode formed on the first region;
a seventh electrode formed on the first region;
an eighth electrode formed on the first region,
a second region formed in the substrate, the second region surrounding a first region in a plan view and having a second impurity region having the first conductivity type;
a dielectric film separating the first impurity region and the second impurity region;
a ninth electrode formed on the second region, the ninth electrode facing the first electrode across the first side;
a tenth electrode formed on the second region, the tenth electrode facing the second electrode across the first side;
an eleventh electrode formed on the second region, the eleventh electrode facing the third electrode across the second side;
a twelfth electrode formed on the second region, the twelfth electrode facing the fourth electrode across the second side;
a thirteenth electrode formed on the second region, the thirteenth electrode facing the fifth electrode across the third side;
a fourteenth electrode formed on the second region, the fourteenth electrode facing the sixth electrode across the third side;
a fifteenth electrode formed on the second region, the fourteenth electrode facing the seventh electrode across the fourth side;
and
a sixteenth electrode formed on the second region, the sixteenth electrode facing the eighth electrode across the fourth side,
wherein the first impurity region is formed to overlap each electrode formed in the first region,
the second impurity region is formed to overlap each electrode formed in the second region, and
the well is formed in the first region and the second region, a portion of the well separating the first impurity region and the second impurity region acting as a resistor between the first impurity region and the second impurity region to protect the semiconductor device from electro-static discharge.

21 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/126,473Filed 23 May 2008 · division
Priority: JP 2004-1091621 Apr 2004
Published: US 2008/0224219 A118 Sep 2008
Granted: 13 Dec 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification2 codes

H10D 89/911
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using passive elements as protective elements
H10D
Inorganic electric semiconductor devices

Family

Application11/095,709Parent of this division · filed 31 Mar 2005
US 2008/0224219 A1Pre-grant publication · published 18 Sep 2008
US 7,394,134 B2Parent of this division
US 2005/0218454 A1Published application
US 8,076,748 B2This patent

From the US filing history. Foreign family members aren’t listed.