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US 8,076,728 B2Granted
Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production
AssigneeInfineon Technologies AG
InventorsKai Esmark, Harald Gossner, Christian Russ, Jens Schneider
Life of this patent
Estimating the term…
Abstract
A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.
Claims9
A method of operating an integrated circuit arrangement, the method comprising:
- biasing a reference operating potential line to a basic potential;
- and
- biasing a positive operating potential line to a more positive potential in comparison with the basic potential;
- wherein
- the integrated circuit arrangement includes a capacitor connected between the operating potential lines, said capacitor including the following regions:
- a basic doping region doped in accordance with a basic doping with a basic doping type and including a region with a maximum dopant concentration;
- at least one connection region doped in accordance with a connection doping with the basic doping type, the maximum dopant concentration of said connection region being higher than the maximum dopant concentration in the basic doping region, wherein said connection region adjoins the basic doping region;
- an electrode region arranged at a distance from the basic doping region;
- and
- a dielectric arranged between the electrode region and the basic doping region;
- in which either given an n-type basic doping type the connection region is electrically conductively connected to the positive operating potential line and the electrode region is electrically conductively connected to the reference operating potential line, or
- in which case given a p-type basic doping type the connection region is electrically conductively connected to the reference operating potential line and the electrode region is electrically conductively connected to the positive operating potential line.
9 more elements
A method of operating an integrated circuit arrangement, the method comprising:
- biasing a reference operating potential line to a basic potential;
- and
- biasing a positive operating potential line to a more positive potential in comparison with the basic potential;
- wherein the integrated circuit arrangement includes:
- a capacitor connected between the operating potential lines, said capacitor including the following regions:
- a basic doping region doped in accordance with a basic doping with a basic doping type and including a region with a maximum dopant concentration;
- at least one connection region doped in accordance with a connection doping with the basic doping type, the maximum dopant concentration of said connection region being higher than the maximum dopant concentration in the basic doping region;
- an electrode region arranged at a distance from the basic doping region;
- and
- a dielectric arranged between the electrode region and the basic doping region, wherein a surface of the dielectric is in contact with a surface of the basic doping region;
- in which either given an n-type basic doping type the connection region is electrically conductively connected to the positive operating potential line and the electrode region is electrically conductively connected to the reference operating potential line, or
- in which case given a p-type basic doping type the connection region is electrically conductively connected to the reference operating potential line and the electrode region is electrically conductively connected to the positive operating potential line.
9 more elements
Dependencies are inferred from the claim text.