Structures for and method of silicide formation on memory array and peripheral logic devices

#The technology disclosed relates to high-density integrated circuits. In particular, the technology disclosed relates to the fabrication of memory cells and their associated peripheral circuits in integrated circuit devices that include non-volatile memory.

#There is a present need to increase the operational speed of non-volatile memory devices. To accomplish this, various techniques have been implemented in device processing and structural designs. For example, reducing the feature dimensions of non-volatile memory devices typically increases their operational speed. Another way of accomplishing this involves reducing the spacing between the memory cell control gates by fabricating bit lines that may serve as transistor sources and/or drains. The operational speed of non-volatile memory devices has also been increased by minimizing the spacing between contacts. Siliciding the gate structures of a memory array has also increased operational speed by reducing gate electrical resistance, thus reducing response delays. In some cases, siliciding has been achieved by employing a self-aligned process referred to in the art as saliciding.

#Bit line shorting as a result of a salicide process has been a problem in some prior art manufacturing processes. For example, U.S. Pat. No. 6,566,194, issued May 20, 2003, discloses “processes for doping and saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the method, word lines are doped prior to patterning the poly layer from which the word lines are formed in the core region. Thereby, the poly layer protects the substrate between the word lines from doping that could cause shorting between bit lines. According to another aspect of the method, word lines are exposed while spacer material, dielectric, or like material protects the substrate between word lines. The spacer material or dielectric prevents the substrate from becoming salicided in a manner that, like doping, could cause shorting between bit lines.” (U.S. Pat. No. 6,566,194, Abstract)

#FIG. 1 is a block diagram of an integrated circuit device including a charge trapping memory array and other circuitry.

#FIG. 2 is a schematic diagram depicting a portion of a virtual ground memory array comprising charge trapping memory elements.

#FIG. 3 shows a layout or plan view of a portion of a virtual ground memory array comprising charge trapping memory elements.

#The following detailed description is made with reference to embodiments illustrated by the figures. These embodiments are described to illustrate the method, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the best mode description that follows.

#FIG. 1 shows a simplified block diagram of integrated circuit 10 fabricated in accordance with the technology discussed herein. Integrated circuit 10 includes a memory array 12. The memory array 12 includes charge trapping memory cells, and bit line contact regions covered by the material used for charge trapping structures that act as silicide masks. A word line decoder 14 is coupled to word lines 16, and a bit line decoder 18 is coupled to bit lines 20, to permit operations that comprise reading data from, and writing data to, the non-volatile memory cells of array 12. To perform operations on memory array 12, addresses may be supplied on address lines 22 to word line decoder 14 and bit line decoder 18. Data-in and data-out structures 24 are coupled to bit line decoder 18 via data bus 26. Data is supplied via a data-in bus 28 from input/output ports on integrated circuit 10, or from other data sources internal or external to integrated circuit 10, to the data-in structures in block 24.

#Other circuitry 30 may be included on integrated circuit 10, such as a general purpose microprocessor or circuitry specific to one or more applications, or a combination of circuit modules providing functionality comprising data storage by memory array 12. Data is supplied via a data-out bus 32 from the sense amplifiers in block 24 to input/output ports on integrated circuit 10, or to other data destinations internal or external to integrated circuit 10. A controller 34 implemented in this example, controls the application of supply voltages charge pumps 36, to perform operations such as read, program, erase, erase verify and program verify voltages on the memory cells of memory array 12. Controller 34 may be implemented using special-purpose logic circuitry as known in the art.