A method for manufacturing a semiconductor device having, on a semiconductor substrate, a first region, the first region including therein a memory cell formation region having a plurality of memory cells formed therein, and a peripheral region including a plurality of MISFET's formed therein outside the first region, the method comprising the steps of:
- (a) forming a first well of a first conductivity type and a second well of a second conductivity type opposite to the first conductivity type in a portion of the semiconductor substrate in the peripheral region;
- (b) forming a first insulation film over the semiconductor substrate in the first region and the peripheral region, and forming a first gate insulation film including the first insulation film in the peripheral region;
- (c) forming a first conductive film over the first insulation film;
- (d) patterning the first conductive film, and thereby forming a pair of first dummy gate pairs being in the first region and interposing the memory cell formation region, and extending in a first direction, and a pair of second dummy gate pairs being in the first region and interposing the memory cell formation region, and extending in a second direction crossing with the first direction, and further leaving a portion of the first conductive film formed in the peripheral region outside the first region;
- (e) after the step (d), forming a third well of the first conductivity type in the semiconductor substrate;
- (f) after the step (e), forming a second insulation film over the semiconductor substrate including over the first dummy gate pairs and the second dummy gate pairs;
- (g) forming a second conductive film over the second insulation film;
- (h) forming an antireflection film over the second conductive film;
- (i) forming a first resist film over the antireflection film;
- (j) patterning the first resist film;
- (k) processing the second conductive film using the first resist film patterned as a mask, and thereby forming a memory gate electrode in each of the memory cells;
- and
- (l) after the step (k), processing the first conductive film formed in the peripheral region, and thereby forming a gate electrode in each of the MISFET's,
- wherein the step (a) includes a step (m) of forming a fourth well of a second conductivity type opposite to the first conductivity type in a region being in a portion of the semiconductor substrate in the first region and deeper than the third well, and forming a fifth well of the second conductivity type in such a manner as to reach the fourth well in a portion of the semiconductor substrate overlapping in plan view with a region including the first dummy gate pairs formed therein,
- wherein the step (l) includes a step (n) of forming an opening in a part of the first dummy gate pairs, and exposing the fifth well through the bottom of the opening, and
- wherein the method further comprises the steps of:
- (o) after the step (n), forming a second semiconductor region of the second conductivity type in the fifth well exposed through the opening;
- (p) forming a second silicide layer over the surface of the second semiconductor region;
- (q) after the step (p), forming an interlayer insulation film over the semiconductor substrate;
- (r) forming a second contact hole penetrating through the interlayer insulation film through the inside of the opening, and reaching the second silicide layer at the bottom;
- and
- (s) embedding a conductive film in the second contact hole, and thereby forming a second plug electrically coupled with the second silicide layer formed over the surface of the second semiconductor region.