Millimeter-wave wideband voltage controlled oscillator

A voltage controlled oscillator-phase lock loop (VCO-PLL) system comprising:

• a control circuit;
• a voltage controlled oscillator (VCO) system implementing a four-channel architecture configured to operate at millimeter wave frequencies, wherein two bands support two channels each, the VCO system comprising:
• a first cross-coupled oscillator system adapted to receive a source voltage;
• the first cross-coupled oscillator system comprising:
• a first transistor comprising a first source, a first gate, and a first drain, the first source coupled to a source voltage, the first gate coupled to a control circuit;
• a first inductor coupled at a first end to the first drain of the first transistor;
• a second inductor coupled at a first end to the first drain of the first transistor;
• a first varactor coupled between the second end of the first inductor and a first tuning voltage controlled by the control circuit;
• a second varactor coupled between the second end of the second transistor and the first tuning voltage controlled by the control circuit;
• a second transistor comprising a second source, a second gate, and a second drain, the second drain coupled to the second end of the first inductor, the second gate coupled the second end of the second inductor, and the second source coupled to a ground signal;
• and
• a third transistor comprising a third source, a third gate, and a third drain, the third drain coupled to the second end of the second inductor, the third gate coupled the second end of the first inductor, and the third source coupled to the ground signal;
• a second cross-coupled oscillator system adapted to receive the source voltage, the second cross-coupled oscillator system comprising:
• a fourth transistor comprising a fourth source, a fourth gate, and a fourth drain, the fourth source coupled to the source voltage, the fourth gate coupled to the control circuit;
• a third inductor coupled at a first end to the fourth drain of the fourth transistor;
• a fourth inductor coupled at a first end to the fourth drain of the fourth transistor;
• a third varactor coupled between the second end of the third inductor and a second tuning voltage controlled by the control circuit;
• a fourth varactor coupled between the second end of the fourth inductor and the second tuning voltage controlled by the control circuit;
• a fifth transistor comprising a fifth source, a fifth gate, and a fifth drain, the fifth drain coupled to the second end of the third inductor, the fifth gate coupled the second end of the fourth inductor, and the fifth source coupled to the ground signal;
• and
• a sixth transistor comprising a sixth source, a sixth gate, and a sixth drain, the sixth drain coupled to the second end of the fourth inductor, the sixth gate coupled the second end of the third inductor, and the sixth source coupled to the ground signal;
• and
• a first isolation buffer system adapted to protect the first cross-coupled oscillator system, the first isolation buffer system generates a first buffer output, the first isolation buffer system comprising:
• a first buffer transistor comprising a first buffer transistor source, a first buffer transistor gate, and a first buffer transistor drain, the first buffer transistor drain coupled to a first buffer voltage, the first buffer transistor gate coupled to the second drain of the second transistor of the first cross-coupled oscillator system;
• and
• a first buffer capacitor coupled between the first buffer transistor source and the first buffer output;
• a second isolation buffer system adapted to protect the first cross-coupled oscillator system, the second isolation buffer system generates a second buffer output, the second isolation buffer system comprising:
• a second buffer transistor comprising a second buffer transistor source, a second buffer transistor gate, and a second buffer transistor drain, the second buffer transistor drain coupled to the first buffer voltage, the second buffer transistor gate coupled to the third drain of the third transistor of the first cross-coupled oscillator system;
• and
• a second buffer capacitor coupled between the second buffer transistor source and the second buffer output;
• a third isolation buffer system adapted to protect the second cross-coupled oscillator system, the third isolation buffer system generates a third buffer output, the third isolation buffer system comprising:
• a third buffer transistor comprising a third buffer transistor source, a third buffer transistor gate, and a third buffer transistor drain, the third buffer transistor drain coupled to a second buffer voltage, the third buffer transistor gate coupled to the fifth drain of the fifth transistor of the second cross-coupled oscillator system;
• and
• a third buffer capacitor coupled between the third buffer transistor source and the third buffer output.
• a fourth isolation buffer system adapted to protect the second cross-coupled oscillator system, the fourth isolation buffer system generates a fourth buffer output, the fourth isolation buffer system comprising:
• a fourth buffer transistor comprising a fourth buffer transistor source, a fourth buffer transistor gate, and a fourth buffer transistor drain, the fourth buffer transistor drain coupled to the second buffer voltage, the fourth buffer transistor gate coupled to the sixth drain of the sixth transistor of the second cross-coupled oscillator system;
• and
• a fourth buffer capacitor coupled between the fourth buffer transistor source and the fourth buffer output;
• a phase-locked-loop (PLL) system;
• and
• a mixer system,
• wherein the first buffer output of the first isolation buffer system is coupled to the third buffer output of the third isolation buffer system;
• and
• wherein the second buffer output of the third isolation buffer system is coupled to the fourth buffer output of the fourth isolation buffer system.