Method and system for use of TSPC logic for high-speed multi-modulus divider in PLL

A system for signal processing, the system comprising:

• a fractional-N phase-locked-loop (PLL) synthesizer that comprises a divider and a VCO;
• said divider enables generation of a divider signal from an output reference signal generated from said VCO, wherein said divider comprises at least one divider stage that utilizes true single phase clock (TSPC) logic D flip-flops for dividing said VCO output reference signal, wherein said TSPC logic comprises a NAND gate coupled to a D input of said D flip-flops;
• said divider enables re-synchronization of said VCO output reference signal and said divider signal, wherein said divider comprises at least two re-synchronization stages that utilize a TSPC logic D flip-flop;
• and
• said divider feeds back said generated divider signal within said fractional-N PLL synthesizer to produce said VCO output reference signal.

A system for signal processing, the system comprising:

• a D flip-flop integrated within at least one divider stage in a divider utilized by a fractional-N phased-locked-loop (PPL) synthesizer;
• said D flip-flop utilizes true single phase clock (TCPC) logic comprising a NAND gate coupled to a D input of said D flip-flop;
• and
• said D flip-flop enables communication of a received clock signal to at least a p-type transistor in a first D flip-flop circuit stage and an n-type transistor in a final D flip-flop circuit stage, wherein a source of said p-type transistor is not directly connected to Vdd and a source of said n-type transistor is not directly connected to ground.

A system for signal processing, the system comprising:

• a D flip-flop integrated within at least one re-synchronization stage in a divider utilized by a fractional-N phased-locked-loop (PLL) synthesizer;
• said D flip-flop utilizes true single phase clock (TCPC) logic comprising a NAND gate coupled to a D input of said D flip flop;
• and
• said D flip-flop enables communication of a received clock signal to at least a p-type transistor in a first D flip-flop circuit stage and an n-type transistor in a final D flip-flop circuit stage, wherein a source of said p-type transistor is not directly connected to Vdd and a source of said n-type transistor is not directly connected to ground.