Semiconductor memory device and method of manufacturing the same

A semiconductor memory device manufacturing method comprising:

• in a semiconductor substrate having a first region and a second region, forming a first gate insulating film on the semiconductor substrate in the first region and forming a second gate insulating film on the semiconductor substrate in the second region;
• forming a first gate wiring material on the first gate insulating film and the second gate insulating film;
• forming a first element isolation insulating film by partially removing the first gate wiring material, the first gate insulating film, and the semiconductor substrate and forming a second element isolation insulating film by partially removing the first gate wiring material, the second gate insulating film, and the semiconductor substrate;
• making a first height from an upper surface of the semiconductor substrate to an upper surface of the first element isolation insulating film smaller than a second height from the upper surface of the semiconductor substrate to an upper surface of the second element isolation insulating film by removing an upper portion of the first element isolation insulating film;
• forming a second gate wiring material in the first region, forming a third gate wiring material in the second region, and making upper surfaces of the second gate wiring material and the third gate wiring material flush with each other;
• and
• forming a first mask layer on the second gate wiring material and forming a second mask layer on the third gate wiring material;
• forming a first gate wiring formed from the first gate wiring material and the second gate wiring material by patterning the first mask layer, the first gate wiring material, the second gate wiring material, the first gate insulating film and the first element isolation insulating film;
• and
• forming a second gate wiring formed from the first gate wiring material and the third gate wiring material by patterning the second mask layer, the first gate wiring material, the third gate wiring material, the second gate insulating film and the second element isolation insulating film,
• wherein the first element isolation insulating film has a first portion and a second portion,
• the second element isolation insulating film has a third portion and a fourth portion,
• the first portion has a first upper surface higher than the upper surface of the semiconductor substrate and a first bottom surface lower than the upper surface of the semiconductor substrate, and is located in a lower part the first gate wiring,
• the second portion has a third upper surface equal to the upper surface of the semiconductor substrate in height and a third bottom surface equal to the first bottom surface in depth, and is located except for the lower part the first gate wiring,
• the third portion has a second upper surface higher than the upper surface of the semiconductor substrate and a second bottom surface lower than the upper surface of the semiconductor substrate, and is located in a lower part the second gate wiring, and
• the fourth portion has a fourth upper surface equal to the upper surface of the semiconductor substrate in height and a fourth bottom surface equal to the second bottom surface in depth, and is located except for the lower part the second gate wiring.