Method of protecting integrated circuits
AssigneeAnalog Devices, Inc.
InventorAlan O'Donnell
Life of this patent
Estimating the term…
Abstract
The present application relates to the manufacture of Wafer Level Chip Scale Packages (WLCSPs), which are a type of CSP in which the traditional wire bonding arrangements are dispensed with in favor of making direct contact by means of conductive bumps (typically solder balls) to the integrated circuitry. WLCSPs differ from fine pitch Ball Grid Array (BGA) and leadframe based Chip Scale Packages (CSPs) in that most of the packaging process steps are performed at wafer level. A package and method of manufacture are provided which prevent the ingress of light to the internal circuitry of WLCSP packages by providing a substantially opaque coating on the inactive side of the WLCSP packages and at least partially on the sides of WLCSP packages.
Claims25
A Wafer Level Chip Scale Package (WLCSP) comprising:
- a substrate comprising:
- an active face;
- a non-active face opposing the active face;
- an active silicon area between the active face and the non-active face, wherein contacts to the active silicon area are provided on the active face;
- and
- a plurality of sides between the active face and the non-active face, wherein at least one side comprises a step, wherein the step extends along a vertical axis from the non-active face towards the active face to a depth that does not reach a level of the active silicon area, and wherein at least a portion of the step extends over the active silicon area along a horizontal axis;
- a side coating of an encapsulant provided in the step, wherein an outer wall of the side coating is defined by a singulation cut that separates the active silicon area from a wafer;
- and
- a layer of the encapsulant covering the non-active face,
- wherein the layer and the side coating protect at least a portion of the active silicon area.
A Wafer Level Chip Scale Package (WLCSP) comprising:
- a substrate comprising:
- an active face;
- a non-active face opposing the active face;
- an active silicon area between the active face and the non-active face, wherein contacts to the active silicon area are provided on the active face;
- and
- a plurality of sides between the active face and the non-active face, wherein at least one side comprises a step, wherein the step extends along a vertical axis from the non-active face towards the active face to a depth that does not reach a level of the active silicon area, and wherein at least a portion of the step extends over the active silicon area along a horizontal axis;
- a side coating of an encapsulant provided in the step, wherein an outer wall of the side coating is defined by a singulation cut that separates the active silicon area from a wafer;
- and
- a light-resistant layer of the encapsulant covering the non-active face,
- wherein the light-resistant layer and the side coating protect at least a portion of the active silicon area.
A Wafer Level Chip Scale Package (WLCSP) comprising:
- a substrate comprising:
- an active face;
- a non-active face opposing the active face;
- an active silicon area between the active face and the non-active face, wherein contacts to the active silicon area are provided on the active face;
- and
- a plurality of sides between the active face and the non-active face, wherein at least one side comprises a step, wherein the step extends along a vertical axis from the non-active face towards the active face to a depth that does not reach a level of the active silicon area, and wherein at least a portion of the step extends over the active silicon area along a horizontal axis;
- a light-resistant side coating of an encapsulant provided in the step, wherein an outer wall of the side coating is defined by a singulation cut that separates the active silicon area from a wafer;
- and
- a layer of the encapsulant covering the non-active face,
- wherein the layer and the light-resistant side coating protect at least a portion of the active silicon area.
A Wafer Level Chip Scale Package (WLCSP) comprising:
- a substrate comprising:
- an active face;
- a non-active face opposing the active face;
- an active silicon area between the active face and the non-active face, wherein contacts to the active silicon area are provided on the active face;
- and
- a plurality of sides between the active face and the non-active face, wherein at least one side comprises a step, wherein the step extends along a vertical axis from the non-active face towards the active face to a depth that does not reach a level of the active silicon area, and wherein at least a portion of the step extends over the active silicon area along a horizontal axis;
- a side coating of an encapsulant provided in the step, wherein an outer wall of the side coating is defined by a singulation cut that separates the active silicon area from a wafer;
- and
- a layer of the encapsulant covering the non-active face,
- wherein layer is continuous and contiguous with the side coating, and wherein the layer and the side coating protect at least a portion of the active silicon area.
Dependencies are inferred from the claim text.