Semiconductor apparatus having a triple well structure and manfacturing method thereof
AssigneeFujitsu Semiconductor Limited
InventorTakuji Tanaka
Life of this patent
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Abstract
A semiconductor apparatus according to the present invention includes a first well-region and a second well-region in a semiconductor substrate, and a plurality of transistors formed to the second well-region. Further, the semiconductor apparatus includes a through-hole region that is formed so as to pierce through the first well-region and enables the second well-region to be electrically conductive to the semiconductor substrate on the bottom of the second well. Furthermore, in the semiconductor apparatus, the border of the through-hole region is arranged between the transistors, and is also arranged to be planarity apart from the transistor.
Claims5
A semiconductor apparatus comprising:
- a semiconductor substrate that is entirely a first conductive type;
- a first well-region of a second conductive type that is formed in a surface layer of the semiconductor substrate;
- a second well-region of the first conductive type that is formed in the surface layer of the semiconductor substrate, a bottom surface of the second well-region and a side surface of the second well-region being in contact with the first well-region;
- a transistor that is formed in the second well-region, the transistor being an MOS transistor having a source region and a drain region;
- and
- a through-hole region that is formed to be pierced through the first well-region, and enables the bottom surface of the second well-region to be electrically conductive to the semiconductor substrate,
- wherein the MOS transistor is arranged above the through-hole region, the MOS transistor being arranged planarily inside of the through-hole region, the border of the through-hole region is arranged to be planarily apart from the MOS transistor, and the source region and the drain region of the MOS transistor is arranged to be apart from the first well-region.
A manufacturing method of a semiconductor apparatus comprising:
- forming a first well-region of a second conductive type in the semiconductor substrate having a first-conductive-type;
- forming a second well-region of the first conductive type in the first well-region in the semiconductor substrate;
- forming a plurality of transistors in the first well-region;
- and
- forming a through-hole region that enables the bottom surface of the second well-region to be electrically conductive to the semiconductor substrate, the through-hole region being formed to be pierced through the first well-region,
- wherein the border of the through-hole region is arranged between the transistors, and is arranged to be planarily apart from the transistor,
- wherein the transistor is arranged above the through-hole region, the transistor being arranged planarily inside of the through-hole region.
A manufacturing method of a semiconductor apparatus comprising:
- forming a first well-region of a second conductive type in the semiconductor substrate having a first-conductive-type;
- forming a second well-region of the first conductive type in the first well-region in the semiconductor substrate;
- forming a plurality of transistors in the second well-region;
- and
- forming a through-hole region that enables the bottom surface of the second well-region to be electrically conductive to the semiconductor substrate, the through-hole region being formed to be pierced through the first well-region,
- wherein the border of the through-hole region is arranged between the transistors, and is arranged to be planarily apart from the transistor,
- wherein the transistor is arranged above the through-hole region, the transistor being arranged planarily inside of the through-hole region.
Dependencies are inferred from the claim text.