Thermoelectric cooler for semiconductor devices with TSV
AssigneeTaiwan Semiconductor Manufactuirng Company
InventorsShih-Cheng Chang, Hsin-Yu Pan
Life of this patent
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Abstract
A thermoelectric structure for cooling an integrated circuit (IC) chip comprises a first type superlattice layer formed on top of the IC chip connected to a first voltage, and a second type superlattice layer formed on the bottom of the IC chip connected to a second voltage, the second voltage being different from the first voltage, wherein an power supply current flows through the first and second type superlattice layer for cooling the IC chip.
Claims19
A thermoelectric structure for cooling an integrated circuit (IC) chip, the thermoelectric structure comprising:
- a first type superlattice layer formed on top of the IC chip connected to a first voltage;
- and
- a second type superlattice layer formed on the bottom of the IC chip connected to a second voltage, the second voltage being different from the first voltage,
- wherein an active conducting current flows through the first and second type superlattice layer for cooling the IC chip.
A thermoelectric structure for cooling an integrated circuit (IC) chip, the thermoelectric structure comprising:
- a P type superlattice layer formed on top of the IC chip connected to a first voltage;
- and
- an N type superlattice layer formed on the bottom of the IC chip connected to a second voltage, the second voltage being higher than the first voltage,
- wherein an active conducting current flows through the N type and the P type superlattice layer for cooling the IC chip.
A thermoelectric structure for cooling an integrated circuit (IC) chip, the thermoelectric structure comprising:
- an N type superlattice layer formed on top of the IC, chip connected to a first voltage;
- and
- a P type superlattice layer formed on the bottom of the IC chip connected to a second voltage, the second voltage being lower than the first voltage,
- wherein an active conducting current flows through the N type and the P type superlattice layer for cooling the IC chip.
Dependencies are inferred from the claim text.