Protection element and fabrication method for the same

#This application claims priority under 35 U.S.C. §119 on Patent Application No. 2006-011478 filed in Japan on Jan. 19, 2006, the entire contents of which are hereby incorporated by reference.

#The present invention relates to a protection element of a semiconductor device formed on a semiconductor substrate and a fabrication method for such a protection element.

#Japanese Laid-Open Patent Publication No. 59-125654 describes a technology in which in a conventional semiconductor memory device including a MOS capacitor and a field effect transistor as an information memory unit (memory cell), a MOS capacitor having an insulating film of which breakdown voltage is relatively low compared with that of the MOS capacitor of the memory cell is used as a protection element.

#FIG. 1A is a diagrammatic plan view of a protection element of a nonvolatile semiconductor memory device in Embodiment 1 of the present invention, and FIG. 1B is a cross-sectional view taken along line Ib-Ib of FIG. 1A.

#FIG. 2A is a diagrammatic plan view of a protection element of a nonvolatile semiconductor memory device in Embodiment 2 of the present invention, and FIGS. 2B and 2C are respectively cross-sectional views taken along line IIb-IIb and line IIc-IIc of FIG. 2A.

#FIGS. 3A and 3B are views showing the protection element in Embodiment 2 of the present invention, taken along line IIIa-IIIa and line IIIb-IIIb, respectively, of FIG. 2A.

#Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In these drawings, components having substantially the same functions are denoted by the same reference numerals for simplification of description. It should be noted that the present invention is not limited to the embodiments to follow.

#FIG. 1A is a plan view diagrammatically showing a protection element of a nonvolatile semiconductor memory device in Embodiment 1 of the present invention, and FIG. 1B is a cross-sectional view taken along line Ib-Ib of FIG. 1A.

#In the plan view of FIG. 1A, a MONOS memory cell is formed in an area where two bit lines 11 and a word line 12 cross each other. The MONOS memory cell includes a gate electrode and a gate insulating film made of an ONO film composed of a silicon oxide film 22, a silicon nitride film 23 and a silicon oxide film 24. Although omitted in FIG. 1A, memory cell transistors are generally arranged in an array in a memory cell region A.