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US 8,026,536 B2Granted
Semiconductor device having a dummy gate
AssigneeElpida Memory, Inc.
InventorKazuhiro Yoshida
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a plurality of MOS transistors, wherein each of the MOS transistors has a drain region, a pair of source regions sandwiching therebetween the drain region, and a pair of normal gates each overlying a space between the drain region and a corresponding one of the source regions. A plurality of dummy gates are provided each between adjacent two of the MOS transistors. The dummy gate electrodes are maintained at an equi-potential with the adjacent drain regions. MOS transistors include a row of pMOS transistors and nMOS transistors, wherein each of pMOS transistors and a corresponding nMOS transistor configure a CMOS gate, and a plurality of CMOS gates configure a ring oscillator.
Claims15
A semiconductor device comprising:
- a semiconductor substrate;
- a plurality of MOS transistors arranged on the semiconductor substrate in a row and each including a drain region, a pair of source regions, and a pair of normal gate electrodes, which are arranged in a direction of the row, the pair of source regions sandwiching therebetween the drain region, each of the normal gate electrodes overlying a space between the drain region and a corresponding one of the source regions;
- a plurality of dummy gate electrodes each overlying a space between one of the source regions of one of the MOS transistors and one of the source regions of an adjacent one of the MOS transistors, each of the dummy gate electrodes being maintained at an equi-potential with the one of the source regions of the one or the adjacent one of the MOS transistors by electrically connecting the each of dummy gate electrodes with the one of the source regions of the one or the adjacent one of the MOS transistors;
- and
- a plurality of source-side interconnects, each of the source-side interconnects being connected to adjacent two of the source regions sandwiching therebetween one of the dummy gate electrodes, the each of the source-side interconnects overlies one of the dummy gate electrodes, the each one of the source-side interconnects is disposed between each of two adjacent transistors, the each one of the source-side interconnects has a width smaller than a total width of the adjacent two of the source regions,
- wherein the normal gate electrodes and the dummy gate electrodes of all of the transistors have the same gate width.
3 more elements
A semiconductor device, comprising:
- a first transistor including a first source region, a second source region, a first drain region, a first gate electrode sandwiched between the first source region and the first drain region, and a second gate electrode between the second source region and the first drain region;
- a second transistor including a third source region, a fourth source region, a second drain region, a third gate electrode sandwiched between the third source region and the second drain region, and a fourth gate electrode sandwiched between the fourth source region and the second drain region;
- a third transistor including a fifth source region, a sixth source region, a third drain region, a fifth gate electrode sandwiched between the fifth source region and the third drain region, and a sixth gate electrode sandwiched between the sixth source region and the third drain region;
- a first dummy gate electrode provided between the second source region of the first transistor and the third source region of the second transistor and electrically connected to at least one of the second source region of the first transistor and the third source region of the second transistor;
- and
- a second dummy gate electrode provided between the fourth source region of the second transistor and the fifth source region of the third transistor and electrically connected to at least one of the fourth source region of the second transistor and the fifth source region of the third transistor,
- wherein the first dummy gate electrode is electrically connected to both of the second source region of the first transistor and third source region of the second transistor, the second dummy gate electrode being electrically connected to both of the fourth source region of the second transistor and the fifth source region of the third transistor.
4 more elements
A semiconductor device, comprising:
- a first diffusion region;
- a second diffusion region;
- a first gate electrode sandwiched between the first and second diffusion regions;
- a third diffusion region;
- a first dummy gate electrode sandwiched between the second and third diffusion regions, and electrically connected to at least one of the second and third diffusion regions;
- a fourth diffusion region;
- a second gate electrode sandwiched between the third and fourth diffusion regions;
- a fifth diffusion region;
- a third gate electrode sandwiched between the fourth and fifth diffusion regions;
- a sixth diffusion region;
- a second dummy gate electrode sandwiched between the fifth and sixth diffusion regions, electrically connected to at least one of the fifth and sixth diffusion regions
- a seventh diffusion region;
- and
- a fourth gate electrode sandwiched between the sixth and seventh diffusion regions,
- wherein the first dummy gate electrode is electrically connected to both of the second and third diffusion regions and the second dummy gate electrode is electrically connected to both of the fifth and sixth diffusion regions.
12 more elements
Dependencies are inferred from the claim text.