Tunnel field effect transistor and method of manufacturing same
AssigneeIntel Corporation
InventorsNiti Goel, Wilman Tsai, Jack Kavalieros
Life of this patent
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Abstract
A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.
Claims25
A tunnel field effect transistor comprising:
- a substrate;
- a source region over the substrate;
- a drain region over the substrate;
- a channel region between the source region and the drain region;
- and
- a gate region adjacent to the channel region,
- wherein:
- the source region contains a first semiconducting material;
- the channel region contains a second semiconducting material;
- the second semiconducting material exhibits type-II band alignment with the first semiconducting material;
- and
- the drain region contains a material having a charge neutrality level that lies above a bottom of its conduction band.
A method of manufacturing a tunnel field effect transistor, the method comprising:
- providing a substrate;
- selecting a first semiconducting material that has type-II band alignment with a second semiconducting material;
- forming a first semiconducting region containing the first semiconducting material;
- forming a second semiconducting region containing the second semiconducting material;
- forming a third semiconducting region containing a third semiconducting material that has a charge neutrality level lying above a bottom of its conduction band;
- depositing a gate insulator over at least a portion of at least the first semiconducting region;
- forming a gate electrode over the gate insulator;
- and
- forming a gate contact, a source contact, and a drain contact for the tunnel field effect transistor.
A tunnel field effect transistor comprising:
- a substrate;
- a source region over the substrate;
- a drain region over the substrate;
- a channel region between the source region and the drain region;
- and
- a gate region adjacent to the channel region,
- wherein:
- the source region contains a first semiconducting material;
- the channel region contains a second semiconducting material;
- the second semiconducting material exhibits type-II band alignment with the first semiconducting material;
- and
- the first semiconducting material and the second semiconducting material are lattice matched to each other.
A tunnel field effect transistor comprising:
- a substrate;
- a source region over the substrate;
- a drain region over the substrate;
- a channel region between the source region and the drain region;
- and
- a gate region adjacent to the channel region,
- wherein:
- the source region contains GaAs0.5Sb0.5;
- the channel region contains In0.53Ga0.47As;
- and
- the drain region contains In0.53Ga0.47As.
A tunnel field effect transistor comprising:
- a substrate;
- a source region over the substrate;
- a drain region over the substrate;
- a channel region between the source region and the drain region;
- and
- a gate region adjacent to the channel region,
- wherein:
- the source region contains a first semiconducting material;
- the channel region contains a second semiconducting material;
- the second semiconducting material exhibits type-II band alignment with the first semiconducting material;
- a junction of the source region and the channel region comprises a tunneling junction of the tunnel field effect transistor;
- the tunnel field effect transistor further comprises a delta layer comprising GaAs0.08Sb0.92 at the tunneling junction;
- the delta layer comprises a material that lowers a valence band offset and a band gap at the tunneling junction;
- and
- the delta layer is fully strained.
A method of manufacturing a tunnel field effect transistor, the method comprising:
- providing a substrate;
- selecting a first semiconducting material that has type-II band alignment with a second semiconducting material;
- forming a first semiconducting region containing the first semiconducting material;
- forming a second semiconducting region containing the second semiconducting material;
- forming a third semiconducting region containing a third semiconducting material;
- depositing a gate insulator over at least a portion of at least the first semiconducting region;
- forming a gate electrode over the gate insulator;
- forming a gate contact, a source contact, and a drain contact for the tunnel field effect transistor;
- and
- lattice matching the first semiconducting material and the second semiconducting material to each other.
A method of manufacturing a tunnel field effect transistor, the method comprising:
- providing a substrate;
- forming a first semiconducting region containing GaAs0.5Sb0.5;
- forming a second semiconducting region containing In0.53Ga0.47As;
- forming a third semiconducting region containing In0.53Ga0.47As;
- depositing a gate insulator over at least a portion of at least the first semiconducting region;
- forming a gate electrode over the gate insulator;
- and
- forming a gate contact, a source contact, and a drain contact for the tunnel field effect transistor.
Dependencies are inferred from the claim text.