Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
AssigneeMEMC Electronic Materials, Inc.
InventorsRobert J. Falster, Vladimir Voronkov, Gabriella Borionetti
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Abstract
A process for the preparation of low resistivity arsenic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.
Claims18
A process for heat-treating a single crystal silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method to influence the precipitation behavior of oxygen in the single crystal silicon wafer in a subsequent thermal processing step, the single crystal silicon wafer having a front surface, a back surface, a central plane between the front and back surfaces, a front surface layer which comprises the region of a wafer between the front surface and a depth, D1, measured from the front surface and toward the central plane, a bulk layer which comprises the region of the wafer between the central plane and front surface layer, is doped with arsenic or phosphorous, and has a resistivity of less than about 5 mΩ-cm, the process comprising:
- heat-treating the single crystal silicon wafer in an atmosphere comprising a nitrogen-containing gas to increase a density of crystal lattice vacancies in the wafer bulk;
- and
- cooling the heat-treated single crystal silicon wafer such that the wafer bulk is supersaturated with crystal lattice vacancies.
Dependencies are inferred from the claim text.