Method of forming flash memory device
AssigneeHynix Semiconductor Inc.
InventorsHee Soo Kim, Jae Mun Kim
Life of this patent
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Abstract
The present invention relates to a method of forming a flash memory device, which is capable of forming floating gates. According to a method of forming a flash memory device in accordance with the present invention, isolation mask patterns are first formed over a semiconductor substrate. Trenches are formed by performing an etching process using the isolation mask patterns. Isolation layers are formed between the isolation mask patterns, including the insides of the respective trenches. The isolation mask patterns are removed. Tunnel dielectric layers and crystallized first conductive layers are sequentially formed over the exposed semiconductor substrate. A dielectric layer and a second conductive layer are formed over the isolation layers and the first conductive layers.
Claims9
A method of forming a flash memory device, the method comprising:
- forming a screen insulating layer on a semiconductor substrate;
- forming isolation mask patterns over the screen insulating layer;
- forming trenches by performing an etching process using the isolation mask patterns;
- forming isolation layers by filling the trenches with an insulating layer;
- removing the isolation mask patterns to expose the screen insulating layer, thereby protruding a portion of the isolation layers upwardly from the semiconductor substrate;
- cleaning the protruded isolation layers and the screen insulating layer so that a portion of the protruded isolation layers is etched and the screen insulating layer partially remains;
- forming a tunnel dielectric layer along surface of the resultant structure including the protruded isolation layers;
- forming a first crystallized floating gate along a surface of the tunnel dielectric layer and the protruded isolation layers, wherein the first crystallized floating gate is an undoped polysilicon layer;
- forming a second crystallized floating gate over the first crystallized floating gate to fill a gap between the protruded isolation layers, wherein the second crystallized floating gate is a doped polysilicon layer;
- performing a polishing process to expose the protruded isolation layers;
- and
- sequentially forming a dielectric layer and a control gate over a resulting structure after performing the polishing process.
A method of forming a flash memory device, comprising:
- sequentially forming a screen insulating layer and an isolation mask pattern over a semiconductor substrate;
- forming trenches in the semiconductor substrate by etching the screen insulating layer and the semiconductor substrate using the isolation mask pattern;
- forming a wall insulating layer on the entire surface of the semiconductor substrate, including top corners of the semiconductor substrate exposed through the trenches;
- forming isolation layers by filling the respective trenches with an insulating layer, wherein each isolation layer partly protrudes upwardly from the semiconductor substrate;
- cleaning the protruded isolation layers and the screen insulating layer so that a portion of the protruded isolation layers is etched and the screen insulating layer partially remains, thereby widening a gap between the protruded isolation layers;
- forming a tunnel dielectric layer along surface of the resultant structure including the protruded isolation layers;
- forming a first crystallized floating gate over the tunnel dielectric layer, wherein the first crystallized floating gate is an undoped polysilicon layer;
- forming a second crystallized floating gate over the first crystallized floating gate to fill a gap between the protruded isolation layers, wherein the second crystallized floating gate is a doped polysilicon layer;
- removing a portion of the second and first crystallized floating gates to expose the protruded isolation layers;
- and
- sequentially forming a dielectric layer and a control gate along a surface of a resulting structure after removing the portion of the second and first crystallized floating gates.
Dependencies are inferred from the claim text.