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US 8,026,112 B2Granted
Method of manufacturing semiconductor device
AssigneeFujitsu Semiconductor Limited
InventorYoshihisa Iba
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AssigneeFujitsu Semiconductor Limited
InventorYoshihisa Iba
Estimating the term…
A method of manufacturing a semiconductor device includes: forming first conductive layer on semiconductor substrate; forming a magnetic film on the first conductive layer; forming second conductive layer on the magnetic film; forming a first mask layer on the second conductive layer; patterning the second conductive layer; patterning the magnetic film; forming a first insulating film on the first conductive layer to cover side surfaces of the patterned second conductive layer and the patterned magnetic film; forming a second mask layer on the first insulating film to cover the patterned second conductive layer, the patterned magnetic film, and the first insulating film; patterning the first insulating film; patterning the first conductive layer; forming a second insulating film on the semiconductor substrate to cover the patterned second conductive layer, the patterned magnetic film, and the patterned first conductive layer; and forming a third insulating film on the second insulating film.
A method of manufacturing a semiconductor device, the method comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
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Comprising components having three or more electrodes, e.g. transistors: of the field-effect transistor [FET] type
Electronic memory devices
About 4 years 2 months of term left · ends 17 Dec 2030 (estimated)
This application claims the benefit of priority from Japanese Patent Application No. 2009-296224 filed on Dec. 25, 2009, the entire contents of which are incorporated herein by reference.
1. Field
The embodiments discussed herein relate to a method of manufacturing a semiconductor device having magnetic elements.
FIGS. 1A to 1C illustrate an exemplary method of manufacturing an MRAM;
FIGS. 2A to 2C illustrate an exemplary method of manufacturing an MRAM;
FIGS. 3A to 3D illustrate an exemplary method of manufacturing an MRAM;
The memory cell of an MRAM includes selection transistors, an MTJ element, upper and lower electrodes coupled so as to have the MTJ element therebetween, and a magnetic field-generating layer for magnetization reversal by generating a magnetic field in the MTJ element. A spin-injection MRAM may not include the magnetic field-generating layer. In the spin-injection MRAM, a current is allowed to flow between an upper electrode and a lower electrode in the direction perpendicular to the MTJ element (positive direction or negative direction), causing magnetization reversal (current scalability) due to electron spin torque passing through a junction surface of the MTJ element. Since the memory cell of the spin-injection MRAM does not have the magnetic-field-generating layer, the area of the memory cell may be reduced.
In the memory cell of an MRAM, the area of the lower electrode may be larger than that of the upper electrode and than that of the MTJ element. A lower electrode film, an MTJ film, and an upper electrode film are sequentially formed. The upper electrode film and the MTJ film are patterned by etching to form the upper electrode and the MTJ element, and the lower electrode film is patterned to form the lower electrode. When the lower electrode film is patterned in the state that the side surface of the MTJ element is exposed, the MTJ element will be damaged by, for example, plasma in an ashing process of a resist used as a mask for the etching and may be damaged by etching gas in the etching.
After patterning of the lower electrode film by etching, the resist mask used in the etching is removed by ashing to expose a surface covered by the lower electrode film and the surface of a lower layer wiring or a conductive plug. By the ashing, the conductive member such as the lower layer wiring or the conductive plug may be oxidized.