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US 8,020,133 B2Granted
Semiconductor integrated circuit with multi-cut via and automated layout method for the same
AssigneeRenesas Electronics Corporation
InventorKeiichi Nishimuda
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit according to an embodiment of the invention includes a single-cut via 60 and a multi-cut via 30 that includes a first via 30a and a second via 30b. An overhang (OHa or OHb) with respect to at least one of the first via 30a and the second via 30b is smaller than an overhang OH with respect to the single-cut via 60.
Claims6
A semiconductor integrated circuit comprising:
- a first wiring formed on a first wiring layer and prolonged in a first direction;
- a second wiring formed on a second wiring layer and prolonged in a second direction;
- and
- a multi-cut via formed to connect the first wiring to the second wiring, the multi-cut via including a first via and a second via formed in the first direction, a distance between the first via and the second via being longer than a width of the second wiring,
- wherein an overhang with respect to the first via is different from an overhang with respect to the second via.
2 more elements
A layout method of a semiconductor integrated circuit comprising:
- forming, using a layout tool executed by a processor on a computer, a first wiring on a first wiring layer, the first wiring being prolonged in a first direction;
- forming, using the layout tool, a second wiring on a second wiring layer, the second wiring layer being prolonged in a second direction;
- and
- forming, using the layout tool, a multi-out via to connect the first wiring to the second wiring, the multi-cut via including a first via and a second via formed in the first direction, a distance between the first via and the second via being longer than a width of the second wiring,
- wherein an overhang with respect to the first via is different from an overhang with respect to the second via.
2 more elements
Dependencies are inferred from the claim text.