Layout method and layout apparatus for semiconductor integrated circuit
AssigneeRenesas Electronics Corporation
InventorNaohiro Kobayashi
Life of this patent
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Abstract
In a layout method for a semiconductor integrated circuit by using cell library data, a plurality of cell patterns are arranged in a first direction. One of gate patterns in one of the plurality of cell patterns is specified as a reference gate pattern. An additional cell pattern is arranged in a second direction orthogonal to the first direction such that a number of gate patterns within a predetermined area containing the reference gate pattern satisfies a constraint condition.
Claims19
A layout method for a semiconductor integrated circuit by using cell library data, said method comprising:
- arranging a plurality of cell patterns in a first direction, as executed by a computer;
- specifying one of gate patterns in one of said plurality of cell patterns as a reference gate pattern;
- and
- arranging an additional cell pattern in a second direction orthogonal to the first direction such that a number of gate patterns within a predetermined area comprising the reference gate pattern satisfies a constraint condition.
A layout apparatus, comprising:
- a storage unit configured to store cell library data;
- and
- an arrangement and wiring tool configured to arrange a plurality of cell patterns in a first direction, by using the cell library data,
- wherein said arrangement & wiring tool comprises:
- a reference gate specifying section configured to specify one of gate patterns in one of the plurality of cell patterns as a reference gate pattern;
- and
- a layout section configured to arrange an additional cell pattern in a second direction orthogonal to the first direction such that a number of gate patters in a predetermined area comprising the reference gate pattern satisfies a constraint condition.
A non-transitory computer-readable medium which stores instructions which when executed by a computer, cause the computer to realize a layout method for a semiconductor integrated circuit by using cell library data, said layout method comprising:
- arranging a plurality of cell patterns in a first direction;
- specifying one of gate patterns in one of said plurality of cell patterns as a reference gate pattern;
- and
- arranging an additional cell pattern in a second direction orthogonal to the first direction such that a number of gate patterns within a predetermined area comprising the reference gate pattern satisfies a constraint condition.
Dependencies are inferred from the claim text.