OPC models generated from 2D high frequency test patterns
AssigneeTexas Instruments Incorporated
InventorsAshesh Parikh, Willie J. Yarbrough
Life of this patent
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Abstract
A method of generating a scalable OPC model for composing reticle pattern files from IC layouts using 2D test patterns is disclosed. The 2D test patterns include basic features which replicate features found in advanced ICs. Variations of feature dimensions and structure pitches provide measurement data which enables the scalability of the OPC model. A method of checking reticle pattern files for features which cannot be modeled by the scalable OPC model is also disclosed.
Claims17
A method of forming an integrated circuit (IC), the method comprising the steps of:
- generating scalable two-dimensional (2D) optical proximity correction (OPC) model, including the steps of:
- laying out 2D test patterns of basic features occurring in IC layouts, wherein the 2D test pattern includes:
- a set of sloped lines with a plurality of slope angles;
- a set of curved lines with a plurality of curvatures;
- a set of necked lines with a plurality of neck widths;
- a set of right angle lines with a plurality of leg extension lengths;
- and
- a set of tee structures with a plurality of cross-member extension lengths;
- and
- generating the OPC model from measured contours of printed and etched features of the 2D test patterns;
- generating a reticle pattern file using the scalable 2D OPC model;
- generating a reticle using the reticle pattern file;
- and
- forming an IC using the reticle.
A method of forming a reticle for an IC, the method comprising the steps of:
- laying out 2D test patterns of basic features occurring in IC layouts, wherein the 2D test pattern includes:
- a set of sloped lines with a plurality of slope angles;
- a set of curved lines with a plurality of curvatures;
- a set of necked lines with a plurality of neck widths;
- a set of right angle lines with a plurality of leg extension lengths;
- and
- a set of tee structures with a plurality of cross-member extension lengths;
- generating a scalable OPC model from measured contours of printed and etched features of the 2D test patterns;
- applying the scalable OPC model sequentially to layout features of the IC;
- and
- generating reticle pattern elements corresponding to the layout features.
A method of checking an IC layout, the method comprising the steps of:
- laying out 2D test patterns of basic features occurring in IC layouts, wherein the 2D test pattern includes:
- a set of sloped lines with a plurality of slope angles;
- a set of curved lines with a plurality of curvatures;
- a set of necked lines with a plurality of neck widths;
- a set of right angle lines with a plurality of leg extension lengths;
- and
- a set of tee structures with a plurality of cross-member extension lengths;
- generating a scalable OPC model from measured contours of printed and etched features of the 2D test patterns;
- applying the scalable OPC model sequentially to layout features of the IC;
- generating reticle pattern elements corresponding to the layout features;
- and
- identifying a layout feature, if existent, of the IC for which a reticle pattern element cannot be generated using the scalable OPC model.
Dependencies are inferred from the claim text.