Three-terminal metal-oxide-metal capacitor
AssigneeMediatek Inc.
InventorTser-Yu Lin
Life of this patent
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AssigneeMediatek Inc.
InventorTser-Yu Lin
Estimating the term…
An MOM capacitor includes a first metal plate; a second metal plate in close proximity to the first metal plate; a third metal plate in close proximity to the first metal plate, and at least one oxide layer interposed between the first, second and three vertical metal plates. The first, second and third metal plate are connected to three different terminals of an integrated circuit.
A metal-oxide-metal (MOM) capacitor, comprising:
A metal-oxide-metal (MOM) capacitor, comprising:
A capacitor, comprising:
Dependencies are inferred from the claim text.
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Capacitive arrangements or effects of, or between wiring layers: capacitor integral with wiring layers
Having non-planar surfaces, e.g. formed by texturisation: having horizontal extensions
Having non-planar surfaces, e.g. formed by texturisation: having vertical extensions
Generic packages, interconnections, connectors or other constructional details of devices covered by
About 3 years 5 months of term left · ends 12 Mar 2030 (estimated)
1. Field of the Invention
The present invention relates to a semiconductor capacitor, and more particularly, to a compact, three-terminal or multi-terminal metal-oxide-metal (MOM) capacitor.
2. Description of the Prior Art
FIG. 1 illustrates a perspective view of a typical MOM capacitor according to the prior art.
FIG. 2 and FIG. 3 are exemplary equivalent circuit diagrams employing discrete two-terminal MOM capacitors according to the prior art.
FIG. 4 is a perspective view fragmentarily showing a finger-type, three-terminal MOM capacitor in accordance with one embodiment of this invention.
One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. The term “horizontal” as used herein is defined as a plane parallel to the conventional major plane or surface of the semiconductor chip or die substrate, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “over”, and “under”, are defined with respect to the horizontal plane.
As devices become smaller and circuit density increases, it is critical that capacitors maintain their level of capacitance while taking up a smaller floor area on the circuit. Reducing circuit floor plan can improve circuit density and save cost. The compact, integral three-terminal (3T-) MOM capacitors of the embodiments can be used in the exemplary equivalent circuit diagrams shown in FIG. 2 or FIG. 3 to replace the two discrete, two-terminal MOM capacitors. Therefore, it is more area efficient than the prior art. Besides, the MOM capacitor can provide better electrical performance and is less mismatched capacitor.
It is to be understood that the embodiments may be applicable to other circuit designs or applications in addition to the exemplary equivalent circuit diagrams shown in FIG. 2 or FIG. 3. For example, the novel 3T-MOM capacitors of the embodiments can be applied in the capacitor array bank of a digitally controlled crystal oscillator (DCXO) to save a large chip area. As known in the art, crystal oscillators, which are comprised of a crystal generally manufactured from quartz and an active amplifier that provides a negative resistance to perpetuate the oscillation, are widely used because they provide a relatively accurate clock/frequency source. They typically provide a better long-term quality clock than other available clock sources such as ceramic resonators, LC tank circuits, etc. The DCXO is the reference frequency oscillator that compensates for the frequency error of a crystal resonator and generates the reference frequency using both an analog circuit and a digital circuit.