US 8,014,114 B2Granted

Semiconductor integrated circuit

AssigneesSanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.

InventorTetsuo Shimamura

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Abstract

The invention provides a semiconductor integrated circuit preventing an electrostatic breakdown due to a surge voltage applied to a power supply wiring or a ground wiring and preventing noise interference between a digital circuit and an analog circuit. By providing a first electrostatic breakdown protection diode and a first electrostatic breakdown protection bipolar transistor in a first island region, the first electrostatic breakdown protection diode and the first electrostatic breakdown protection bipolar transistor turn on when a surge voltage is applied to a first ground wiring and protect a digital circuit against an electrostatic breakdown. Furthermore, a first isolation layer is contacted with the first ground wiring in a position that is more adjacent to a first ground pad than the digital circuit, and a second isolation layer is contacted with a second ground wiring in a position that is more adjacent to a second ground pad than an analog circuit. This prevents noise interference between the digital circuit and the analog circuit.

A semiconductor integrated circuit comprising:

a semiconductor substrate of a first general conductive type;
a semiconductor layer of a second general conductive type formed on the semiconductor substrate;
a first circuit formed on the semiconductor substrate;
a first ground pad formed on the semiconductor substrate and receiving a ground voltage;
a first ground wiring connecting the first ground pad and the first circuit and supplying the ground voltage to the first circuit;
a first power supply wiring supplying a first power supply voltage to the first circuit;
a first isolation layer of the first general conductivity type formed in the semiconductor layer so as to isolate part of the semiconductor layer from other part of the semiconductor layer as a first island region of the second general conductivity type;
a first electrostatic breakdown protection diode formed between the first power supply wiring and the first ground wiring by connecting the first island region to the first power supply wiring;
a second circuit formed on the semiconductor substrate;
a second ground pad formed on the semiconductor substrate and receiving the ground voltage;
a second ground wiring connecting the second ground pad and the second circuit and supplying the ground voltage to the second circuit;
a second power supply wiring supplying a second power supply voltage to the second circuit;
a second isolation layer of the first general conductivity type formed in the semiconductor layer so as to isolate part of the semiconductor layer from other part of the semiconductor layer as a second island region of the second general conductivity type;
and
a second electrostatic breakdown protection diode formed between the second power supply wiring and the second ground wiring by connecting the second island region to the second power supply wiring,
wherein the first isolation layer is connected to the first ground wiring in a position that is closer to the first ground pad than to the first circuit.

13 more elements

Facts

Application

12/268,709Filed 11 Nov 2008

Priority

JP 2007-29625615 Nov 2007

Published

US 2009/0128971 A121 May 2009

Granted

6 Sep 2011

Term ends

Not estimatedThe source records don’t support an estimate.

Classification3 codes

H10D 89/711
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using bipolar transistors as protective elements
H10D 89/611
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using diodes as protective elements
H10D
Inorganic electric semiconductor devices

Abstract

Claims14