US 8,013,393 B2Granted

Electrostatic discharge protection devices

AssigneeAdvanced Micro Devices, Inc.

InventorsAkram Salman, Stephen Beebe

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Abstract

A method for fabricating a semiconductor device is provided. According to this method, a first gate electrode and a second gate electrode are formed overlying a first portion of a silicon substrate, and ions of a first conductivity-type are implanted into a second portion of the silicon substrate to define a first conductivity-type diode region within the silicon substrate. Ions of a second conductivity-type are implanted into a third portion of the silicon substrate to define a second conductivity-type diode region within the silicon substrate. During one of the steps of implanting ions of the first conductivity-type and implanting ions of the second conductivity-type, ions are also implanted into at least part of the first portion to define a separation region within the first portion. The separation region splits the first portion into a first well device region and a second well device region. The separation region is formed in series between the first well device region and the second well device region.

Claims32

Dependent claims

A device, comprising:

a semiconductor-on-insulator (SOI) structure comprising a carrier wafer, a silicon substrate, and insulating layer is disposed between the carrier wafer and the silicon substrate, comprising:
a first conductivity-type diode region disposed within the silicon substrate and that extends to the insulating layer, wherein the first conductivity-type is P+;
a first well device region disposed within the silicon substrate and that extends to the insulating layer, wherein the first well device region is directly in series with and in physical contact with the first conductivity-type diode region, wherein the first well device region is a first P-well device region;
a P+-type separation region disposed within the silicon substrate and that extends to the insulating layer, wherein the P+-type separation region is in series with the first well device region and has a single P+ conductivity-type;
a second well device region disposed within the silicon substrate and that extends to the insulating layer, wherein the second well device region is in series with the P+-type separation region, wherein the second well device region is a second P-well device region;
a second conductivity-type diode region disposed within the silicon substrate, wherein the second conductivity-type diode region is disposed within the silicon substrate and extends to the insulating layer, wherein the second conductivity-type diode region is in series with the second well device region, wherein the second conductivity-type is N+;
and
a first gate electrode disposed overlying the first well device region of the silicon substrate;
a second gate electrode disposed overlying the second well device region of the silicon substrate;
a circuit to be protected from an electrostatic discharge event;
and
a bias circuit coupled to the first gate electrode and the second gate electrode, wherein the bias circuit comprises:
means for applying a positive bias voltage to both the first gate electrode and the second gate electrode during normal operation, and stopping application of the positive bias voltage to both the first gate electrode and the second gate electrode in response to an electrostatic discharge event.

10 more elements

A device, comprising:

a semiconductor-on-insulator (SOI) structure comprising a carrier wafer, a silicon substrate, and insulating layer is disposed between the carrier wafer and the silicon substrate, comprising:
a first conductivity-type diode region disposed within the silicon substrate and that extends to the insulating layer, wherein the first conductivity-type is P+;
a first well device region disposed within the silicon substrate and that extends to the insulating layer, wherein the first well device region is directly in series with and in physical contact with the first conductivity-type diode region, wherein the first well device region is a first N-well device region;
a P+-type separation region disposed within the silicon substrate and that extends to the insulating layer, wherein the P+-type separation region is in series with the first well device region and has a single P+ conductivity-type;
a second well device region disposed within the silicon substrate and that extends to the insulating layer, wherein the second well device region is in series with the P+-type separation region, wherein the second well device region is a second N-well device region;
a second conductivity-type diode region disposed within the silicon substrate, wherein the second conductivity-type diode region is disposed within the silicon substrate and extends to the insulating layer, wherein the second conductivity-type diode region is in series with the second well device region, wherein the second conductivity-type is N+;
and
a first gate electrode disposed overlying the first well device region of the silicon substrate;
a second gate electrode disposed overlying the second well device region of the silicon substrate;
a circuit to be protected from an electrostatic discharge event;
and
a bias circuit coupled to the first gate electrode and the second gate electrode, wherein the bias circuit comprises:
means for applying a negative bias voltage to both the first gate electrode and the second gate electrode during normal operation, and stopping application of the negative bias voltage to both the first gate electrode and the second gate electrode in response to an electrostatic discharge event.

10 more elements

A device, comprising:

a semiconductor-on-insulator (SOI) structure comprising a carrier wafer, a silicon substrate, and insulating layer is disposed between the carrier wafer and the silicon substrate, comprising:
a first conductivity-type diode region disposed within the silicon substrate and that extends to the insulating layer, wherein the first conductivity-type is P+;
a first well device region disposed within the silicon substrate and that extends to the insulating layer, wherein the first well device region is directly in series with and in physical contact with the first conductivity-type diode region, wherein the first well device region is a first P-well device region;
an N+-type separation region disposed within the silicon substrate and that extends to the insulating layer, wherein the N+-type separation region is in series with the first well device region and has a single N+ conductivity-type;
a second well device region disposed within the silicon substrate and that extends to the insulating layer, wherein the second well device region is in series with the N+-type separation region, wherein the second well device region is a second P-well device region;
a second conductivity-type diode region disposed within the silicon substrate, wherein the second conductivity-type diode region is disposed within the silicon substrate and extends to the insulating layer, wherein the second conductivity-type diode region is in series with the second well device region, wherein the second conductivity-type is N+;
and
a first gate electrode disposed overlying the first well device region of the silicon substrate;
a second gate electrode disposed overlying the second well device region of the silicon substrate;
a circuit to be protected from an electrostatic discharge event;
and
a bias circuit coupled to the first gate electrode and the second gate electrode, wherein the bias circuit comprises:
means for applying a positive bias voltage to both the first gate electrode and the second gate electrode in response to an electrostatic discharge event, and stopping application of the positive bias voltage to both the first gate electrode and the second gate electrode so that the first gate electrode and the second gate electrode are configured to be electrically floating.

10 more elements

A device, comprising:

a semiconductor-on-insulator (SOI) structure comprising a carrier wafer, a silicon substrate, and insulating layer is disposed between the carrier wafer and the silicon substrate, comprising:
a first conductivity-type diode region disposed within the silicon substrate and that extends to the insulating layer, wherein the first conductivity-type is P+;
a first well device region disposed within the silicon substrate and that extends to the insulating layer, wherein the first well device region is directly in series with and in physical contact with the first conductivity-type diode region, wherein the first well device region is a first N-well device region;
an N+-type separation region disposed within the silicon substrate and that extends to the insulating layer, wherein the N+-type separation region is in series with the first well device region and has a single N+ conductivity-type;
a second well device region disposed within the silicon substrate and that extends to the insulating layer, wherein the second well device region is in series with the N+-type separation region, wherein the second well device region is a second N-well device region;
a second conductivity-type diode region disposed within the silicon substrate, wherein the second conductivity-type diode region is disposed within the silicon substrate and extends to the insulating layer, wherein the second conductivity-type diode region is in series with the second well device region, wherein the second conductivity-type is N+;
and
a first gate electrode disposed overlying the first well device region of the silicon substrate;
a second gate electrode disposed overlying the second well device region of the silicon substrate;
a circuit to be protected from an electrostatic discharge event;
and
a bias circuit coupled to the first gate electrode and the second gate electrode, wherein the bias circuit comprises:
means for applying a negative bias voltage to both the first gate electrode and the second gate electrode in response to an electrostatic discharge event, and stopping application of the negative bias voltage to both the first gate electrode and the second gate electrode so that the first gate electrode and the second gate electrode are configured to be electrically floating.

10 more elements

Dependencies are inferred from the claim text.